Il 07/05/2014 04:37, Laszlo Ersek ha scritto:
>
> I'm not familiar with i2c-bus, but from the qemu code, it looks like you
> should check the output of "info mtree". The pc_init1() function calls
> piix4_pm_init() with smb_io_base=0xb100. Again from a superficial
> reading of the code, this should later lead to a 64 bytes wide IO
> register block (at 0xb100):
>
> piix4_pm_initfn()
> pm_smbus_init()
> pm_smbus_init()
> memory_region_init_io()
> memory_region_set_enabled()
> memory_region_add_subregion()
>
> I/O
> 0000000000000000-000000000000ffff (prio 0, RW): io
> 000000000000b100-000000000000b13f (prio 0, RW): pm-smbus
What Laszlo said is correct. In PIIX4, the SMBus registers are not in a
BAR, instead you can read the base I/O address in the PCI configuration
space of the device at 00:01.3, bytes 0x90...0x91 (bit 0 is 1 for I/O
space). Writing 0x9 at byte 0xd2 of the configuration space enables it,
so from Linux you'd have:
$ setpci -s 01.3 0x90.w
0xb101
0xb100 is the default, but it can be changed.
Because they're not in a BAR you probably need to access them directly
without using the PCI support in UEFI. You can use PCI support routines
to access the configuration space.
The ICH9 chipset instead, which is available with "-M q35", has a
separate PCI device at 00:1f.3 and the SMBus registers can be found in
BAR4 therein. OVMF does not support it yet, but in any case you can see
this from "info pci" and "info mtree".
(qemu) info mtree
...
000000000000b100-000000000000b13f (prio 1, RW): pm-smbus
...
(qemu) info pci
...
Bus 0, device 31, function 3:
SMBus: PCI device 8086:2930
IRQ 10.
BAR4: I/O at 0xb100 [0xb13f].
id ""
Note that it is still at 0xb100, but that's a coincidence (or rather, an
explicit choice of the firmware, SeaBIOS in this case).
Paolo
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