On 08/28/14 17:17, Peter Maydell wrote: > On 28 August 2014 16:08, Laszlo Ersek <[email protected]> wrote: >> - Even if someone wants to implement such, where should (where *can*, >> actually) the exception handler table exist at all? The addresses >> that I listed above are backed by the (read-only) flash chip. The >> exception handler table should be built somewhere in DRAM, no? > > There's no inherent reason it needs to be in DRAM. For a > boot loader I would expect it to be a minimal assembly > stub that just sets up to call into C code. If you really > need to have runtime dispatch of your exceptions you > can do it by indirection in the C function. If all you're > doing is "blow up and print message to UART" then you > don't need that either, you can just have your panic > handler live in your ROM image. > > If you want to get fancier then for AArch64 (and for > AArch32 CPUs with support for the security extensions) > there's a CPU register you can use to put the vector > table somewhere else than the base of RAM. But it's > nice to have a functional vector table out of the gate > to deal with things blowing up before you get round to > installing a table that's somewhere else.
You're saying "put the vector table somewhere else than the base of RAM". Address 0 that I described was guest-phys address 0, but it's flash, it's not RAM. The base of RAM would be 1GB (0x4000_0000). I'm confused -- where does the CPU look for the table per default? Address 0 (whatever may be there), or the base of system RAM? Anyway this topic is out of my league :) Thanks, Laszlo ------------------------------------------------------------------------------ Slashdot TV. Video for Nerds. Stuff that matters. http://tv.slashdot.org/ _______________________________________________ edk2-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/edk2-devel
