> On Oct 23, 2014, at 3:53 PM, Bruce Cran <[email protected]> wrote:
>
> I've been looking through BaseLib and found the MemoryFence function.
> I can see the implementations in Ia32/GccInline.c and X64/GccInline.c,
> but I don't see anything for VC++ except the empty function in
> X86MemoryFence.c . There's _ReadWriteBarrier in BaseIoLibIntrinsic
> (the comment in IoLibMsc.c should probably read "...to the compiler
> and does _not_ emit code" - the "not" is currently missing) but
> MemoryFence doesn't appear to make use of it.
>
> Also, since MemoryFence appears similar to the x86 mfence instruction,
> should the documentation be updated to make it clear it's only an
> instruction to the compiler and doesn't issue a CPU fence operation?
The MemoryFence() BaseLib API definition is based on Itanium processor memory
model. So they basically enforce the same memory consistency that you see on
X86.
I can’t think of a UP usage case for X86 mfence on X86, as it solve a complex
MP memory order issue we generally don’t see in EFI. UP does “what you want”
on X86.
__asm__ __volatile__ ("" ::: "memory”); and _ReadWriteBarrier() are
notifications to the compiler about order, and have nothing to do with hardware
as they are just about compiler optimization.
The only thing that having the __asm__ __volatile__ ("" ::: "memory”); would
buy you is it could fix a bug in the calling code (forgetting to make something
volatile etc.). If the calling code is correctly constructed I can’t think of
an issue you we see by not having the _ReadWriteBarrier. It would not hurt to
add the _ReadWriteBarrier to make things constant.
Itanium:
MemoryFence::
mf;; // memory access ordering
// do we need the mf.a also here?
mf.a // wait for any IO to complete?
// not sure if we need serialization here, just put it, in case...
srlz.d;;
srlz.i;;
br.ret.dpnt b0;;
ARM:
ASM_PFX(MemoryFence):
// System wide Data Memory Barrier.
dmb
bx lr
X86 is a no-op.
Thanks,
Andrew Fish------------------------------------------------------------------------------
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