Sheldon,
I think the person that implemented this, a long time ago, is on vacation for
the holidays.
It is important to remember the FAT driver is required to boot by EFI and thus
the size of the driver is also a constraint. It has to fit in the FLASH.
It is also important to remember that EFI’s main job is to quickly boot the
system. Thus there is no mechanism for an orderly shutdown like the OS. When
you hit the power button in the OS it generates an ACPI event and the OS does
an orderly shutdown so the FAT driver can flush any caches (etc.), in EFI the
power just goes away. So the EFI FAT driver may trade off performance to be
more robust.
Thanks,
Andrew Fish
> On Dec 19, 2014, at 1:04 AM, Sheldon Lu <lxd5...@gmail.com> wrote:
>
> Hi Sergey,
>
> Thanks for your reply!
>
> My opinion is:
>
> First, Enhanced FAT driver assigns 512KB(32KB/Page * 16Pages) to FAT Cache
> and 4MB(64KB/Page * 64Pages) to Data Cache.
> The Cache size is fixed. So full cache will not use more memory.
>
> Second, I think cache mechanism should be used to speed up accesses to ranges
> that overlap the cached ranges.
> Let me explain this:
> (1) When you read/write 63~64KB, it actually read/write 0~64KB. That is
> 1:63(1 portion for use and 63 may be wasted).
> (2) When you read/write 64~128KB, whether you cache it or not, you have to
> put the data in a memory buffer(read from disk to buffer or write the buffer
> to disk).
> That means there is no “waste” if you put 64~128 in cache. And next time,
> when you read/write no matter 63~129KB or 63~70KB or 0~192KB, all will hit in
> cache!
>
> So I’m still very confused. It seems to me that “full” cache mechanism is
> “full” benefit.
>
> Looking forward to more discussion!
>
> Thank you
> Sheldon
>
> From: Sergey Isakov [mailto:isakov...@bk.ru]
> Sent: Friday, December 19, 2014 3:20 PM
> To: edk2-devel@lists.sourceforge.net
> Subject: Re: [edk2] a question about cache mechanism in EnhancedFatDxe
>
> Hi,
> I may propose that read data done by 64kb block. So to read first data 63-64
> the driver must read 0-64 and then cache 0-63 for other use.
> The same for tail data. The driver read more then needed and redundant data
> is cached.
> The is no full cache mechanism to speedup data and cache size is small.
>
> Enjoy.
>
> On 19.12.2014, at 6:33, Sheldon Lu wrote:
>
>
> Hi All,
>
> Is there any one can help answer my question ?
> I really need to understand why and explain this to my custmer.
> Please share your ideas or give me some clues if any one knows the answer.
>
> Really thank you!
>
> Sheldon
>
> From: Sheldon Lu [mailto:lxd5...@gmail.com <mailto:lxd5...@gmail.com>]
> Sent: Thursday, December 18, 2014 10:32 AM
> To: edk2-devel@lists.sourceforge.net <mailto:edk2-devel@lists.sourceforge.net>
> Cc: jljus...@intel.com <mailto:jljus...@intel.com>; ruiyu...@intel.com
> <mailto:ruiyu...@intel.com>; GaryLi(李俊); KasalinYi(易花中); RuiDai(戴潇睿)
> Subject: a question about cache mechanism in EnhancedFatDxe
>
> Hi guys,
>
> I am studying the EnhancedFatDxe driver recently. I met a question when
> looking into FatAccessCache() in DiskCache.c. As the "Routine Description"
> says:
> "2. Access of Data cache (CACHE_DATA):
> The access data will be divided into UnderRun data, Aligned data and OverRun
> data;
> The UnderRun data and OverRun data will be accessed by the Data cache,
> but the Aligned data will be accessed with disk directly."
>
> I'm very confused with "the Aligned data will be accessd with disk directly".
> I can't understand why it only caches "unaligned" data but exclude the
> possiblity to cache "aligned" data ? Does it discount the performance ?
>
> An example to show how it works:
>
> If I want to read the data from offset 63KB to offset 129KB(these
> offsets are relative to the Root directry). As the cache alignment is 64KB in
> FAT Data Region, so the data is divided into 3 parts:
>
> 63KB~64KB … 64KB~128KB … 128KB~129KB
>
> The current cache mechanism of EnhancedFatDxe only caches the accesses
> to “63KB~64KB”and “128KB~129KB”,but let the access to “64KB~128KB”goes to
> disk directly!
>
> I’m very confused why it only caches the head and tail but leaves the main
> body behind ?
>
> Any one knows why it is designed like this ? Isn’t it better to cache ALL
> datas without discrimination ?
>
> Looking forward to your reply!
> Thank you so much!
>
> B.R.
>
> Sheldon
>
>
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