Use CPUID Leaf 01 to detect support for CLFLUSH instruction.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off by: Michael Kinney
<michael.d.kin...@intel.com<mailto:michael.d.kin...@intel.com>>
Index: Library/BaseLib/Ia32/FlushCacheLine.asm
===================================================================
--- Library/BaseLib/Ia32/FlushCacheLine.asm (revision 17201)
+++ Library/BaseLib/Ia32/FlushCacheLine.asm (working copy)
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD
License
; which accompanies this distribution. The full text of the license may be
found at
@@ -34,9 +34,20 @@
; );
;------------------------------------------------------------------------------
AsmFlushCacheLine PROC
+ ;
+ ; If the CPU does not support CLFLUSH instruction,
+ ; then promote flush range to flush entire cache.
+ ;
+ mov eax, 1
+ cpuid
mov eax, [esp + 4]
+ test edx, BIT19
+ jz @F
clflush [eax]
ret
+@@:
+ wbinvd
+ ret
AsmFlushCacheLine ENDP
END
Index: Library/BaseLib/Ia32/FlushCacheLine.c
===================================================================
--- Library/BaseLib/Ia32/FlushCacheLine.c (revision 17201)
+++ Library/BaseLib/Ia32/FlushCacheLine.c (working copy)
@@ -1,7 +1,7 @@
/** @file
AsmFlushCacheLine function
- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -36,9 +36,23 @@
IN VOID *LinearAddress
)
{
+ //
+ // If the CPU does not support CLFLUSH instruction,
+ // then promote flush range to flush entire cache.
+ //
_asm {
- mov eax, LinearAddress
+ mov eax, 1
+ cpuid
+ test edx, BIT19
+ jz NoClflush
+ mov eax, [esp + 4]
clflush [eax]
+ jmp Done
+NoClflush:
+ wbinvd
+Done:
}
+
+ return LinearAddress;
}
Index: Library/BaseLib/Ia32/GccInline.c
===================================================================
--- Library/BaseLib/Ia32/GccInline.c (revision 17201)
+++ Library/BaseLib/Ia32/GccInline.c (working copy)
@@ -1,7 +1,7 @@
/** @file
GCC inline implementation of BaseLib processor specific functions.
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
@@ -1745,6 +1745,19 @@
IN VOID *LinearAddress
)
{
+ UINT32 RegEdx;
+
+ //
+ // If the CPU does not support CLFLUSH instruction,
+ // then promote flush range to flush entire cache.
+ //
+ AsmCpuid (0x01, NULL, NULL, NULL, &RegEdx);
+ if ((RegEdx & BIT19) == 0) {
+ __asm__ __volatile__ ("wbinvd":::"memory");
+ return LinearAddress;
+ }
+
+
__asm__ __volatile__ (
"clflush (%0)"
: "+a" (LinearAddress)
@@ -1752,7 +1765,7 @@
: "memory"
);
- return LinearAddress;
+ return LinearAddress;
}
------------------------------------------------------------------------------
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