Hi Olivier, 1. I am looking at the 'ArmPkg/Drivers/TimerDxe/TimerDxe.c' DXE driver and seeing how the timer interrupts are registered:
// Install secure and Non-secure interrupt handlers // Note: Because it is not possible to determine the security state of the // CPU dynamically, we just install interrupt handler for both sec and non-sec // timer PPI Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerVirtIntrNum), TimerInterruptHandler); ASSERT_EFI_ERROR (Status); Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerHypIntrNum), TimerInterruptHandler); ASSERT_EFI_ERROR (Status); Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerSecIntrNum), TimerInterruptHandler); ASSERT_EFI_ERROR (Status); Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum), TimerInterruptHandler); ASSERT_EFI_ERROR (Status); I wanted to understand how the Interrupt registration changes for PPI or SPI interrupt sources. As usually the Virtual, Hypervisor, Physical and Physical Non-Secure interrupts are PPI does the PPI number need to be defined as the PCD values in the same way as linux. The Linux gicv3 documentation says (Documentation/devicetree/bindings/arm/gic-v3.txt): SPI interrupts are in the range [0-987]. PPI interrupts are in the range [0-15]. 2. Also one related question is whether on Juno Rev1, you are able to get the BootDelay to work via timer based events? If yes, can you please share if you achieve this by using the ARMv8 generic timer or the SP804 timer. Regards, Bhupesh ------------------------------------------------------------------------------ _______________________________________________ edk2-devel mailing list edk2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/edk2-devel
