>If you use Joe's solution where PTT is one input into an AND gate, if PTT is >not asserted, your relays will not close. All inputs to the AND gate must be >present for the output to change state.
I've wanted this 'feature request' since K3 Day 1. Don's solution sounds like a reasonable work-around. Unfortunately, I'm transistorially challenged. Can I build this with a few 12AU7s ? Ralph, VE7XF ______________________________________________________________ Elecraft mailing list Home: http://mailman.qth.net/mailman/listinfo/elecraft Help: http://mailman.qth.net/mmfaq.htm Post: mailto:[email protected] This list hosted by: http://www.qsl.net Please help support this email list: http://www.qsl.net/donate.html
