I was wondering if I could get some information from those who have
experience in SRAM cell design and sense amplifiers. I don't have much
experience in this. For fun, I'm trying to build a small SRAM-based
register file that will have two read ports and one write port. The
goal is to read on the positive edge of the clock and write a data on
the negative edge of the clock.

My goal is to try to fabricate this as a test chip on MOSIS AMI  0.5
um using 5V. Naturally, I'm using Electric ;)

My SRAM cell supporting 2 reads, 1 write is as shown here:
http://imagebin.ca/view/1Iwk5z4.html

Although, I should probably run in through SPICE simulation and see if
checks out, I'm fairly sure its OK. I was able to get IRSIM to pass
this. bitA, bitB are precharged to logic high before the word lines
are asserted. If the cell contains a 0, the bitlines will begin to
discharge. The write is done through bitC where both data and data_b
are required on the access transistors.

The problem is the sense amplifier. I'm been reading a few books
including Dr. Baker's. However, the sense amplifiers there operate on
bit and bitb (bit bar lines). In my schematic, I have a single line
for reading. Consequently, an initial try of my sense amplifier is as
follows:

http://imagebin.ca/view/4zGSFZQ.html

The main issue is VDD connection on the left side of the schematic
which ties the output of the inverter to 1. I'm not sure if the left
inverter is even necessary here? Because if bit is 1, sense_bit should
be 1. However, if the line is beginning to discharge (i.e. bit is
going from VDD -> 0), sense_bit should be 0. Is there a better way to
design the sense amplifier that works only only a single line? Can Dr.
Baker comment on this?

The phis is the sense clock which when activated isolates the sense
amplifier from the rest of the SRAM cells through the PMOS isolation
transistor on the right.

Thanks for any insights anybody might have.
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