On Nov 4, 5:15 pm, Jake Baker <[email protected]> wrote:
> Hi Pallav,
>
> I took a quick look at your SRAM cell. The use of fully-differential
> bit lines is used in most SRAMs to speed up the sensing. Single-ended
> designs can be used but they won't be as fast. Also, putting the read
> circuit in the memory cell will (dramatically) increase the size of
> the SRAM cell. However, the benefit is that you get plenty of signal
> out at bitA and bitB. You may be able to drive the cell single-ended
> and reduce the cell's size but the pass transistor's increase in width
> and the driver's size increase to ensure reliable writing may make
> this approach less attractive. Anyway since you are pre-charging those
> lines just wait a little time after driving WordA or WordB high and
> then clock the signal at BitA or BitB into a latch. You don't need
> another regenerative latch for sensing. So why is a fully-differential
> design faster? Because in the single-ended design you have to wait
> until the bitline discharges, if it's going to discharge, more than
> VDD/2. Using fully differential signals you simply need a large enough
> delta-V between the bitlines. Also, common-mode noise is, ideally,
> removed using fully-differential sensing.
>
> Hope this helps, Jake.
>
>
>
> On Wed, Nov 4, 2009 at 1:17 PM, pallav <[email protected]> wrote:
>
> > I was wondering if I could get some information from those who have
> > experience in SRAM cell design and sense amplifiers. I don't have much
> > experience in this. For fun, I'm trying to build a small SRAM-based
> > register file that will have two read ports and one write port. The
> > goal is to read on the positive edge of the clock and write a data on
> > the negative edge of the clock.
>
> > My goal is to try to fabricate this as a test chip on MOSIS AMI 0.5
> > um using 5V. Naturally, I'm using Electric ;)
>
> > My SRAM cell supporting 2 reads, 1 write is as shown here:
> >http://imagebin.ca/view/1Iwk5z4.html
>
> > Although, I should probably run in through SPICE simulation and see if
> > checks out, I'm fairly sure its OK. I was able to get IRSIM to pass
> > this. bitA, bitB are precharged to logic high before the word lines
> > are asserted. If the cell contains a 0, the bitlines will begin to
> > discharge. The write is done through bitC where both data and data_b
> > are required on the access transistors.
>
> > The problem is the sense amplifier. I'm been reading a few books
> > including Dr. Baker's. However, the sense amplifiers there operate on
> > bit and bitb (bit bar lines). In my schematic, I have a single line
> > for reading. Consequently, an initial try of my sense amplifier is as
> > follows:
>
> >http://imagebin.ca/view/4zGSFZQ.html
>
> > The main issue is VDD connection on the left side of the schematic
> > which ties the output of the inverter to 1. I'm not sure if the left
> > inverter is even necessary here? Because if bit is 1, sense_bit should
> > be 1. However, if the line is beginning to discharge (i.e. bit is
> > going from VDD -> 0), sense_bit should be 0. Is there a better way to
> > design the sense amplifier that works only only a single line? Can Dr.
> > Baker comment on this?
>
> > The phis is the sense clock which when activated isolates the sense
> > amplifier from the rest of the SRAM cells through the PMOS isolation
> > transistor on the right.
>
> > Thanks for any insights anybody might have.
>
> --http://CMOSedu.com/jbaker/jbaker.htm
Hi Dr. Baker,
Thank you for this clear explanation. I will try out the fully-
differential design and see if I can get it to work.
Kind regards.
pallav
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