Hi Group, I've made some progress in my SRAM design. I'm working on the SRAM control circuitry to generate the appropriate pulses for the read/ write operation so I can finally tie all the individual components together. My timing diagram looks something like this: http://imagebin.ca/view/RhEJoII.html
Basically, precharge is done at the end so that the next read can begin immediately in the next clock cycle. I'm trying to generate a pulse for the precharge (phip = 0 will activate the precharge circuitry). I don't see any better way than using the main clock and generating it from that. My Electric circuit looks like this: http://imagebin.ca/view/0m_9emcQ.html Simulating in SPICE gave me a pretty good result: http://imagebin.ca/view/hYBZLh.html I just need to add some buffers at the output to delay the signal until 8ns when the precharge operation should begin Questions: 1. Is there a better way or circuit to generate such pulses? 2. For the inverters, I'm using lengths/widths of 3 for the NMOS/PMOS to get weak gates. For MOSIS C5N fabrication, are there any issues in changing the length? Would a length of 10 be valid for a design? 3. Has anyone experienced any significant issues with using minimum sized transistors (W=3/4) with AMI C5N process? I think now its supported by ON Semi. Thanks for any ideas. Kind regards. --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [email protected] For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en -~----------~----~----~----~------~----~------~--~---
