Hi Group,

I'm testing out a small SRAM-based register file circuit. I've got the
basic building blocks down and they seem to be OK (passing simple
IRSIM tests individually), but I'm having some difficultly testing the
entire thing out.

I'm attaching my entire Electirc files/IRSIM files. My top circuit
looks like this:

http://imagebin.ca/view/e15GJn.html

I have a simple case where initially I'm trying to write 00 to
register 0 (my circuit has 4 2-bit registers, organized in 2 columns).
The I/O buffers are able to drive the data on the bit lines OK, I get
01 on sense0/sense0_b and 01 on sense1/sense1_b. However, I am
expecting to get the same on so0/so0_b, so1/so1_b but I end up getting
a bunch of Xs in IRSIM simulation. I don't know if this is a problem
with my differential amplifier or if there is a special way to drive
bidirectional bitlines in IRSIM? I've purposefully made the write
buffer very big to be able to drive the bitlines but I'm not sure why
I'm getting Xs. The precharge circuity is disabled and so is the sense
amplifier so what could be the problem?

I've asserted the proper word line (wordC0 =1) and the proper columns
multiplexer (sel0=1, sel1=0). Thus, eventually, t0/t0_b and t1/t1_b
should end up being 01 as well.

Here is the IRSIM waveform output:

http://imagebin.ca/view/KfwHjB.html

As you can see, my clock is as follows:

clock phip 1 1 0
clock phis 1 0 1
clock phis_b 0 1 1

The first phase is for reading, second phase is for writing, third
phase is for precharging the bitlines for the next operation.

I'm attaching the entire Electric jelib/IRSIM test files in case any
one has any idea what I'm doing wrong? Since I'm on a Mac, I have some
difficulty getting finding a decent SPICE simulator but will try to
run them through HSPICE at work.

Any ideas of what I'm doing wrong will be most help. Thanks for your
time.

Kind regards.
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