I wanted to play around with designing some basic I/O pads for the TSMC 0.18 um process in Electric. Looking at MOSIS website, there are generic guidelines http://mosis.com/Technical/Designrules/scmos/scmos-glass.html.
Does someone have access to better documentation for bonding sizes particular to TSMC 0.18um? Has anyone designed pads for this process that they'd be willing to share? Thanks for your time. -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
