Hi Priyanka, Thanks a lot for this. This will be very helpful.
Kind regards. On Dec 3, 6:22 pm, priyanka parikh <[email protected]> wrote: > Hello Dr.Pallav, > > I have designed both analog and digital pads with TSMC .18 um process. The > attached jelib contains both the pads and respective padframes. I am still > working on testing of the padframes and the documentation as well. The > document should be ready by early next year. > > Good luck! > > Thanks, > Priyanka. > > > > On Thu, Dec 3, 2009 at 2:52 PM, pallav <[email protected]> wrote: > > I wanted to play around with designing some basic I/O pads for the > > TSMC 0.18 um process in Electric. Looking at MOSIS website, there are > > generic guidelines > >http://mosis.com/Technical/Designrules/scmos/scmos-glass.html. > > > Does someone have access to better documentation for bonding sizes > > particular to TSMC 0.18um? Has anyone designed pads for this process > > that they'd be willing to share? > > > Thanks for your time. > > > -- > > > You received this message because you are subscribed to the Google Groups > > "Electric VLSI Editor" group. > > To post to this group, send email to [email protected]. > > To unsubscribe from this group, send email to > > [email protected]<electricvlsi%[email protected]> > > . > > For more options, visit this group at > >http://groups.google.com/group/electricvlsi?hl=en. > > -- > Regards, > Priyanka. > > MOSIS_DEEP_PADS_CL018_ESD.jelib > 487KViewDownload -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
