> I am planning to Layout the design of BGR in electric which i have > simulated, its on TSMC 130nm CMOS process and TSMC 180 nm both . Can > any body help me with the Technology file of this process. I can edit > the technology file for this Process but if some body have this > technology then please help me with this .
TSMC 180 nm from MOSIS supports Scalable CMOS rules (which is the deafult in Electric) so you can use that. TSMC 130, however, uses only TSMC rules which will be provided by the vendor (usually through signing an NDA). Maybe someone knows how to convert them/export them into Electric for use. See the MOSIS website for more information. -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
