It's fairly easy, see attached. I used a Pure Node for the n-well (use special select to select/edit) then put pAct nodes on the left/right (exported as E and C) then an nWell node in the middle (Exported as B). I didn't put the substrate connections to ground, that you would want to have, around the PNP. Note that you can't make a lateral NPN in an n-well process but you can in a p-well process hence why I used a PNP.
For the schematic I placed wire pins and exported them as E, B, and C then used the open polygon and a triangle for the symbol. Hope this helps, Jake. On Mon, Jan 25, 2010 at 10:22 PM, oliverks <[email protected]> wrote: > I want to develop some unusual transistor topologies. For example, > Designing Analog Chips by Hans Camenzind talks about lateral PNP > transistors with split connectors (see fig 1-17 page 1-23 of > > http://www.designinganalogchips.com/_count/countdown.pl?designinganalogchips.pdf > ) > > Is this possible to do in Electric? > > What is the recommend approach? > > What I really want is the ability to create a new cell with a symbol > and layout that allows me to define a new device type. > > Oliver > > -- > You received this message because you are subscribed to the Google Groups > "Electric VLSI Editor" group. > To post to this group, send email to [email protected]. > To unsubscribe from this group, send email to > [email protected]<electricvlsi%[email protected]> > . > For more options, visit this group at > http://groups.google.com/group/electricvlsi?hl=en. > > -- http://CMOSedu.com/jbaker/jbaker.htm -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
lateral_NPN.jelib
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