On Jan 31, 11:25 am, Jake Baker <[email protected]> wrote: > Hi All, > > In the attached library please see the schematic view of the cell R_divider > (the only schematic in the library). > > When I do an ERC Well Check on this schematic I get 4 errors, > > ERC Well Check error 1 of 4: N-Well contact is floating > > Is this a bug? > > Thanks, Jake. > > P.S. Yes, one could argue that the well check should only be used on layouts > but I feel it should also work for schematics in most cases. > > --http://CMOSedu.com/jbaker/jbaker.htm > > tutorial_1.jelib > 2KViewDownload > > jb_electricPrefs.xml > 8KViewDownload
One student I'm co-advising in China has also mentioned he is seeing some ERC errors. Unfortunately, he can't access Google groups so is unable to post. Here is what he said (I've asked him to send me a list of errors so we can track this down). "Secondly, about the ECR->check wells, you say there might be a bug in the ERC code, I also think so for I do the cnfet layout in the electricBinary-8.09,I run the ERC- >check wells, there are no errors, but in the electricBinary-8.10,there are lots of errors. It like we do the creating new technologies." Also is there somewhere where the latest Electric code with all the current bug fixes can be checked out? It gets difficult to cut/paste hacks from these forum. I think Dr. Baker's suggestion is correct. Even if the user applies ERC on a schematic, it shouldn't go haywire. Hopefully, this can be fixed if it is a problem. thanks pallav -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
