> I am using the mocmos technology. When I put down a nfet or pfet and > look at in 3D View the solid green rectangle (which I am assuming is > the n or p implant volume) appears to run completely under the poly- > silicon rectangle. Is this correct?
Well, wherever the polysilicon intersects the n/p active regions, that is where the gate is formed. > Both FETs show a darker volume surrounding the green area. Should I > assume this represents the depletion region? Finally I see the light > gray volume surrounding the whole device. I assume this is the > substrate material, but then again may be it is the well material in > the pFet case. I don't think the 3D view shows the depletion region, oxide, etc... It is just showing the nwell/pwell, the select region, the active region, and the polysilicon. > > I am also a little confused on what the difference is between the > nWell and pWell nodes and the nAct and pAct nodes. Do I just use the > nWell and pWell nodes to tie the body connections to the correct > voltage level? The pwell/nwell nodes are 'substrate taps' used to connect substrate/ nwell to GND/VDD, respectively. The nAct/pAct contact nodes are for connecting the active region of the nmos/pmos transistor to metal1. > When I use pFets I assume I need to place down an nWell. Does this > get done automatically by Electric or do I need to place a pure nWell > down first? You will notice that in the mocmos technology Electric already provides n-Transistor and p-Transistor. It already contains the appropriate well information so there is nothing you have to do. Of course, if you are creating your own transistors, you will have to provide that information, but why reinvent the wheel? > > And finally I can place pure pWells down. Is this something that is > allowed in most processes? Can I places this in an nWell? Where > would I use this? Depending upon the process, in general, the substrate is pwell. For pMOS transistor, you create the n-well, before adding the p+ region. They two regions can't overlap each other, otherwise, it is a DRC error in Electric. The pure well nodes are just there to get rid of some errors that Electric complains about (for example, nwell and pwell separated by 2-3 lambda). Hope this helps. pallav -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
