Hi
I am trying to connect the bus like the following
connect a bus in[1:200] to two cells one from in[1:100] which has 100
inputs and the other from [101:200] but both connection comes from one
input pin in[1:200]. but I get the follwing error massage in DRC:
Schematic DRC (full) error 1 of 2: Arc bus['t[1:100]'] (200 wide)
connects to export 't[0:99]' of node delaycell_100_bus{ic}
['delay...@0'] (100 wide)
>=================================663=================================
Schematic DRC (full) error 2 of 2: Arc bus['t[101:200]'] (200 wide)
connects to export 't[0:99]' of node delaycell_100_bus{ic}
['delay...@2'] (100 wide)
)
Thanks
--
You received this message because you are subscribed to the Google Groups
"Electric VLSI Editor" group.
To post to this group, send email to [email protected].
To unsubscribe from this group, send email to
[email protected].
For more options, visit this group at
http://groups.google.com/group/electricvlsi?hl=en.