At 12:55 PM 5/23/2010, you wrote:
Hi I am trying to connect the bus like the following connect a bus in[1:200] to two cells one from in[1:100] which has 100 inputs and the other from [101:200] but both connection comes from one input pin in[1:200]. but I get the follwing error massage in DRC:Schematic DRC (full) error 1 of 2: Arc bus['t[1:100]'] (200 wide) connects to export 't[0:99]' of node delaycell_100_bus{ic} ['delay...@0'] (100 wide) >=================================663================================= Schematic DRC (full) error 2 of 2: Arc bus['t[101:200]'] (200 wide) connects to export 't[0:99]' of node delaycell_100_bus{ic} ['delay...@2'] (100 wide) )
A cell export has a fixed width (yours are 100 wide) and you have to connect a bus of the same width to it.
To split your 200-wide bus into two 100-wide busses, simply create two new bus segments and label them appropriately (in[1:100] and in[101:200]) and then connect these segments to the icons. Busses in Electric can be named many times on many different parts of the circuit and they are understood to all be connected.
Another possibility is to make an array of icons. So, for example, if you have an icon with a 100-wide bus and you make an array of two of them, then you have these choices when connecting to the port:
> Connect with a 100-wide bus and it will connect each of the 100 signals to both of the arrayed icon port signals.
> Connect with a 200-wide bus and it will send the first 100 signals to the first icon and the second 100 signals to the second icon in the array.
-Steven Rubin -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
