Does Electric's DRC for the MOCMOS technology know the MOSIS rules for the silicide block?
If I drop blobs of silicide layer at random locations in my design, Electric's DRC doesn't seem to get upset. Does Electric not know about the design rules for the silicide layer? Also, we have access to the TSMC vendor rules for their 350nm process; these can't be distributed with Electric for licensing reasons. Is there an easy way to have Electric's internal DRC use the vendor rules, or do we need to manually translate the rules into an Electric technology? The latter process is error-prone enough that we might just stick to SCMOS if that's the only way forward. Lastly, I see that there are technologies named "mocmos", "mocmosold", and "mocmossub". For a "deep-submicron" (180nm) design, should we use "mocmossub" or should we use "mocmos" and select "deep submicron" in the preferences? What's the difference between the two? We're going to shoot for a design that passes DRC for both the "submicron" and "deep submicron" rules so that scaling is an option for the next time around. Thanks! -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To view this discussion on the web visit https://groups.google.com/d/msg/electricvlsi/-/dtf_SY2K6igJ. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
