Hi Gilda,
I tried loading the DRC rules, and it didn't work. Attached is the DRC file
I loaded just to check this out.
You can try some arbitrary value and check it out if you want... for
example, you could try minimum metal width to be 2.4um (2 lambda)
Thank you,
Deepak
On Thu, Aug 16, 2012 at 4:28 PM, gildav <[email protected]> wrote:
> Deepak
>
> The xml tech doesn't have any drc rule so I don't see how it could have
> reached the code in the exception below (at least with the simple example I
> created)
>
> Gilda
>
> Deepak Sekar wrote, on 8/15/12 2:58 PM:
>
> Hi Gilda,
>
> Thanks for helping out.
>
> Attached is the xml file for my new technology.
>
> Deepak
> PS: I'll be glad to provide a consulting fee for any time you spend on
> this. If you're interested in the opportunity, please do let me know at
> [email protected]
>
>
>
>
> -------------------------------------------------------------------------------------------------------------
> On Tuesday, August 14, 2012 10:08:25 AM UTC-7, Gilda wrote:
>>
>> Deepak
>>
>> Can I have access to your new tech? The exception below might suggest
>> that something is not OK with it.
>>
>> Thanks
>>
>> Gilda
>>
>> Deepak Sekar wrote, on 8/13/12 4:45 PM:
>> > Hi,
>> >
>> > I've created a new technology by editing the existing nMOS technology
>> > in Electric. I'm unable to run DRC on it though, it says "Exception
>> > caught" and gives me the following error message. Has anyone
>> > encountered this issue yet? Any countermeasures?
>> >
>> > Thank you,
>> > Deepak
>> > ------------------------------**------------------------------**------------------
>>
>> > Running DRC with area bit on, extension bit on
>> > Checking again hierarchy .... (0.0 secs)
>> > Found 10 networks
>> > Checking cell 'nmos{lay}'
>> > java.lang.AssertionError
>> > at com.sun.electric.tool.drc.DRC.**cropActiveArc(DRC.java:106)
>> > at com.sun.electric.tool.drc.**Quick.checkArcInst(Quick.java:**855)
>>
>> > at
>> > com.sun.electric.tool.drc.**Quick.checkThisCell(Quick.**java:547)
>>
>> > at com.sun.electric.tool.drc.**Quick.doCheck(Quick.java:336)
>> > at
>> > com.sun.electric.tool.drc.**Quick.checkDesignRules(Quick.**java:157)
>>
>> > at com.sun.electric.tool.drc.DRC$**CheckDRCHierarchically.doIt(
>> **DRC.java:
>> > 1465)
>> > at com.sun.electric.tool.EThread.**run(EThread.java:117)
>> >
>>
>> --
> You received this message because you are subscribed to the Google Groups
> "Electric VLSI Editor" group.
> To view this discussion on the web visit
> https://groups.google.com/d/msg/electricvlsi/-/wP0Iwe08y-sJ.
> To post to this group, send email to [email protected].
> To unsubscribe from this group, send email to
> [email protected].
> For more options, visit this group at
> http://groups.google.com/group/electricvlsi?hl=en.
>
>
> --
> You received this message because you are subscribed to the Google Groups
> "Electric VLSI Editor" group.
> To post to this group, send email to [email protected].
> To unsubscribe from this group, send email to
> [email protected].
> For more options, visit this group at
> http://groups.google.com/group/electricvlsi?hl=en.
>
--
You received this message because you are subscribed to the Google Groups
"Electric VLSI Editor" group.
To post to this group, send email to [email protected].
To unsubscribe from this group, send email to
[email protected].
For more options, visit this group at
http://groups.google.com/group/electricvlsi?hl=en.
<?xml version="1.0" encoding="UTF-8"?>
<!--
Document: DRC deck for Technology supertex
Generated by: Electric (9.01)
-->
<!DOCTYPE DRCRules SYSTEM "DRC.dtd">
<DRCRules>
<Foundry name="NONE">
<LayerRule ruleName="7.1 Mercury" layerName="Metal" type="MINWID" when="ALL" value="2.0"/>
</Foundry>
</DRCRules>
