Can anybody guide me step by step to generate layout from my verilog code using Electric Silicon Compiler. I tried using the help available in the manual but could not succeed. Let us take the example of a following code:
module AOI (out, a, b, c, d); output out; input a, b, c, d; wire m, n, p; and g1 (m, a, b); and g2 (n, c, d); or g3 (p, m, n); not g4 (out, p); endmodule -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to electricvlsi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
