I have developed a cell library and Javascript tool enabling conversion from VHDL via the Xilinx Wepback tool and VLSI Design Silicon compiler to a chip layout. These tools are publicly available.
An example of a UART is here: https://personalpages.hs-kempten.de/~vollratj/Microelectronics/2016_12_00_00_Synthesis_UART.html Best Regards Joerg Vollrath -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to electricvlsi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
