On Wed, 20 Jul 2011, Jon Elson wrote:
Date: Wed, 20 Jul 2011 20:41:44 -0500
From: Jon Elson <el...@pico-systems.com>
Reply-To: EMC developers <emc-developers@lists.sourceforge.net>
To: EMC developers <emc-developers@lists.sourceforge.net>
Subject: Re: [Emc-developers] Preempt-RT ... where to put the patches ?
Viesturs L??cis wrote:
Out of curiosity I tried to find results for D510 and D525 boards -
they both are mentioned in the list of tested systems.
This is D510:
https://www.osadl.org/Latency-plot-of-system-in-rack-1-slot.qa-latencyplot-r1s4.0.html?latencies=&showno=&slider=228
This is D525:
https://www.osadl.org/Latency-plot-of-system-in-rack-4-slot.qa-latencyplot-r4s7.0.html?latencies=&showno=&slider=228
Where did they get 4 cores? From hyperthreading? Do I understand
correctly that disabling hyperthreading should improve latency
figures?
Yup, the D510 is a CATASTROPHE, the D525 is just really bad. You could
probably run a servo machine
Well 100 uSec of jitter should be perfectly acceptable _if_ the PID
(or hardware stepgen) corrections were based on actual time instead of thread
invocation time, heck even 500 uSec jitter might be OK.
on the D525, but it isn't real good. Yes, I think the extra "CPUs" are
from hyperthreading, and disabling
it should help.
Jon
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