Max,
Here are a couple of additional ideas based on two or
your comments:
My suggested stackup:
%> S
%> S
%> G
%> P
%> S
%> S
%> P
%> G
%> S
%> S
Max's question: I wonder how this compares with this type of stackup?
S
G
S
S
P
G
S
S
G
S
The benefit of Max's stackup is that the top and bottom layers have a
return plane on the next lower layer. Also, his still retains a distributed
board capacitance design in the middle two layers. Another benefit is that
there
is an additional ground plane. This should further lower ground plane
impedance and associated ground bounce. The benefit of my suggested
stackup is that there is roughly twice the board distributed
capacitance. I think I prefer Max's stackup unless there is a lot of
300+ MHz RF due to poor decoupling.
%>I never thought of lining the perimeter of the board with caps. Is that
%>how you do it?
I've never thought of it either. The point of the technique is that if you
have
traces jumping a split in the power plane, the RF return current path on
the power plane can be shunted to the ground plane to cross the gap,
and on the other side, shunted back up to the power plane to continue
the journey back to the source. This should cut down the loop area of
the current path. This path is created by physically puting the decoupling
caps at either edge of the split as close to the trace that jumps the gap as
possible. This suggestion is far from optimum as there is only a narrow
frequency band that the decoupling is of a low impedance. By using
several carefully chosen values of cap, I would think that the
useful frequency range of the technique could be widened.
It is not clear that lining the perimeter of the board with caps would do
any more good than if the same number and value of caps are
place anywhere else on the board. According to the most recent
research I have read, the most important thing to do in placing
decoupling is to get the via inductance as low as possible so that the
resonant frequency of the discrete decoupling circuit is as high as
possible. . Since a ground plane and power plane is used, the partial
inductance of the current path along the power and gorund planes is
negligible compared with the via inductance. This assumes that the
power and ground layers are about 10 mils or less apart
Therefore decoupling cap placement is not as critical. As the power
to ground spacing increases significantly above 10 mils, the
ground and power plane partial inductances begin to become
significant vs the via inductance and the placement of the decoupling
capacitors becomes more and more critical. I am paraphrasing a
paper that I read from University Missouri-Rolla -- I hope I didn't
butcher their theory and empirical findings too badly!
Anyway, good luck with the design.
Regards,
[email protected]
----------
From: Max
To: Tony Fredriksson
Cc: mkelson; emc-pstc
Subject: Re: Need EMC Help With Video Card
List-Post: [email protected]
Date: Friday, August 30, 1996 12:11PM
Tony,
Thanks for the great ideas!
%>
%>Hi,
%>One way to do this would be to line the gap with decoupling caps
%>in the vicinity where the traces cross, on either side of the gap. The
%>values of the caps would be chosen so that they self-resonate
%>(due to self AND via series inductance) in the problem frequency range.
%>But 189 MHz is getting up there in frequency. Assuming 8 nH (3 nH
%>per via and 2 nH cap self inductance) a decoupling cap value 100pF is
%>in the ballpark.
I hadn't given any thought to this problem, but now that you mention it, I
have found a spot in Intel's P6 application notes where they recommend doing
the same thing. The problem of course is in trying to get them at the
resonant frequency and there is a chance that the next turn of the card (a
major change) will have a problem at a different harmonic. Still, it's
worth
a try.
%>
%>I don't really like that approach. Instead, I wonder why the route is
%>allowing traces to jump the gap between analog and digital power.
%>I would think that most of the shared circuitry between analog and digital
%>power is within the DAC itself and that if the power planes are well
placed
%>and of the proper shape, there isn't much external route on the board
that
%>needs to intermingle between the two power areas, especially not a clock
%>signal.
We have designed the board so that our DAC power plane doesn't have this
problem. I learned that the hard way! However, the other island involved
is
a 3.3V island in the 5V power plane.
%>
%>Even if power and ground are solid planes, I don't like that layers 1
%>and 8 do not have a return layer adjacent to them. Again, loop area is
%>greater than the optimum value unless you use significant return route
%>on the same layer adjacent to to signal route for any critical signal on
%>these
%>top and bottom layers. If more power and ground layers are not an option,
%>I would rather see the signal layer count DECREASE by two layers
%>using a 6 layer board with your stackup or DECREASE by four layers
%>with the power and ground layers in the middle to take advantage
%>of better distributed capacitance board decoupling.
I agree completely. I have sent a note out saying that the only good
solution is to get the number of signal layers down to four and to add two
additional ground planes.
%>
%>You will get better high frequency decoupling if power and ground
%>are adjacent in the stackup. This is due to the distributed capacitance
%>created by the adjacent planes due to the more closely spaced planes
%>(capacitor "plates"). With the number of signal layers you
%>are using, you would exacerbate the problems of adjacent layer
%>returns if you went to this type of structure. So considering the number
%>of power and ground planes vs. signal layers you have, your current
%>stackup with its deficiencies are your most logical option. Again, for
this
%>many signal layers, I would like to see one more power and one more
%>ground layer with the following stackup.
%>
%> S
%> S
%> G
%> P
%> S
%> S
%> P
%> G
%> S
%> S
I wonder how this compares with this type of stackup?
S
G
S
S
P
G
S
S
G
S
%>
%>I would keep high speed route off of the top and bottom layers as
%>much as possible and would resize the analog and digital planes
%>to avoid high speed signal traces jumping the gap. I would also
%>use vias around the perimeter of the board to stitch the ground planes
%>together every 0.1" or so.
I never thought of lining the perimeter of the board with caps. Is that
how you do it?
%>
%>Furthermore, you can retain the original board cost and improve things
%>further if you can squeeze the signal lines into 4 layers as follows:
%>
%> S
%> G
%> P
%> S
%> S
%> P
%> G
%> S
I wonder how that compares with this kind of stack up?
S
G
S
P
G
S
G
S
I guess the answer depends partially on how well the power plane acts as a
return.
%>
%>Now having said all of that, the above concerns may not be your
%>problem at all and changing all of this may not help. But hey,
%>consider the advice worth what you paid for it!
%>
%>Regards,
%>[email protected]
%>
%> ----------
Thanks Again,
Max
