Hi,
The stackup you describe combined with the split in the power planes is of
concern to me. I have labelled them with numbers as shown below
to discuss a few issues.
The stackup is:
S (layer 1)
S (layer 2)
P (layer 3)
S (layer 4)
S (layer 5)
G (layer 6)
S (layer 7)
S (layer 8)
The power and ground plane act as signal return for RF signals.
They can be considered as equivalent returns if they are "shorted"
together and at the same potential (i.e. they are well decoupled).
Even if they are well decoupled, layer 3, the power plane, has a split
and it appears from your info that there are traces that cross the gap.
If those traces are on any other layer than layers 5 or 7, you don't
have an adjacent return path that is optimized and are creating a
larger than optimal return loop. The power plane with the split can
be improved for this scenario if the decoupling is excellent. If it
is done right, it is possible that traces jumping the gap on layers
2 and 4 can find a suitable short path down to the ground return layer
through the decoupling caps and then back up to the power layer
on the other side of the gap to the power layer.
One way to do this would be to line the gap with decoupling caps
in the vicinity where the traces cross, on either side of the gap. The
values of the caps would be chosen so that they self-resonate
(due to self AND via series inductance) in the problem frequency range.
But 189 MHz is getting up there in frequency. Assuming 8 nH (3 nH
per via and 2 nH cap self inductance) a decoupling cap value 100pF is
in the ballpark.
I don't really like that approach. Instead, I wonder why the route is
allowing traces to jump the gap between analog and digital power.
I would think that most of the shared circuitry between analog and digital
power is within the DAC itself and that if the power planes are well placed
and of the proper shape, there isn't much external route on the board that
needs to intermingle between the two power areas, especially not a clock
signal.
Even if power and ground are solid planes, I don't like that layers 1
and 8 do not have a return layer adjacent to them. Again, loop area is
greater than the optimum value unless you use significant return route
on the same layer adjacent to to signal route for any critical signal on
these
top and bottom layers. If more power and ground layers are not an option,
I would rather see the signal layer count DECREASE by two layers
using a 6 layer board with your stackup or DECREASE by four layers
with the power and ground layers in the middle to take advantage
of better distributed capacitance board decoupling.
You will get better high frequency decoupling if power and ground
are adjacent in the stackup. This is due to the distributed capacitance
created by the adjacent planes due to the more closely spaced planes
(capacitor "plates"). With the number of signal layers you
are using, you would exacerbate the problems of adjacent layer
returns if you went to this type of structure. So considering the number
of power and ground planes vs. signal layers you have, your current
stackup with its deficiencies are your most logical option. Again, for this
many signal layers, I would like to see one more power and one more
ground layer with the following stackup.
S
S
G
P
S
S
P
G
S
S
I would keep high speed route off of the top and bottom layers as
much as possible and would resize the analog and digital planes
to avoid high speed signal traces jumping the gap. I would also
use vias around the perimeter of the board to stitch the ground planes
together every 0.1" or so.
Furthermore, you can retain the original board cost and improve things
further
if you can squeeze the signal lines into 4 layers as follows:
S
G
P
S
S
P
G
S
Now having said all of that, the above concerns may not be your
problem at all and changing all of this may not help. But hey,
consider the advice worth what you paid for it!
Regards,
[email protected]
----------
From: Max
To: Tony Fredriksson
Cc: emc-pstc; mkelson
Subject: Re: Need EMC Help With Video Card
List-Post: [email protected]
Date: Thursday, August 29, 1996 10:19AM
%>
%>
%>Max,
%>
%>At what frequency or band of frequencies is the problem occuring?
Our video clock operates at 126 Mhz. The frequency synthesizer seems to be
deriving this from a 31.5 Mhz clock, so it produces harmonics at 31.5,
63.0, 95.5, 126.0, 157.5, 189.0 220.5, 252,0, 283.5, 315.0, 346.5, etc.
The only frequency that I am having problems with right now is 189.0.
However, this is an interim version of the card. So, presumably, different
harmonics could pop up on the next version.
%>
%>When you take the video cable off at the system end, the emission
%>does not change?
%>
%>If you remove the video cable and the emission does not change,
%>are there still other cables attached to the system?
%>
%>If there are other cables attached to the system, have you tried
%>removing them one at a time or in groups to see if there is any
%>one or two that are radiating the emissions?
I still have the problem when I remove all of the cables from the system,
including the printer cable, etc. The emissions are coming out of the
holes in the PC cabinet and this is a very good PC and is well sealed. The
largest emissions seem to be coming from the fan vent holes.
%>
%>Is there video modulation in the signal or does it look like a pure
%>clock emission (narrow band, CW)?
Narrow band.
%>
%>How well is the I/O panel of the connector bonded to the system
%>back panel and how well is the D-shell of the connector tied into
%>the return plane on the board.
I checked this yesterday as the result of someone elses suggestion.
Everything is properly bonded and well bonded. This particular PC also has
EMI gasketing where the card panels mate with the cabinet panel.
%>
%>What method is used to isolate analog and digital power and what
%>type of decoupling are you using on the analog power plane?
A series ferrite with one 33uF and two .01uF and two .1uF caps on the chip
side and about fourteen .01 and .1 uF caps on the otherside of the ferrite.
Come to think of it, I wonder If I should have at least one larger cap in
there--like maybe a 330uf tantalum for instance?
%>
%>Are there traces that cross the gap between analog and digital power
%>and what is the nearest return path in the board stackup for each of
%>these traces , if any? Are the return paths on a layer immediately
%>adjacent to these signal traces and directly underneath (i.e. a ground
%>plane?).
The stackup is:
S
S
P
S
S
G
S
S
And the power plane is broken up into two different voltage islands. So
the signal layers on the power plane side of the board have a long ways to
go to find a return path. I suspect that this is my problem. One idea
might be to put ground traces on the signal layers where the two islands
meet?
%>
%>While from your answer, it sounds like you've done a number of things
%>to determine that it is the card/box combo without cables attached, I
%>am doublechecking.
%>
%>Not that this can be fixed through this e-mail forum, but more info is
%>better.
%>It's good to see that you are smart enough to consider a qualified
%>consultant as another resource to bounce the design off of.
I presently have a dozen different ideas in the fire and little time to
devote to this, so I don't mind paying a good consultant. I have picked up
some good ideas from this group, though. The ones that seem most
reasonable to me are to put an RC filter on the clock lines and to try to
figure out a way to provide a better return for the clock and signal lines.
%>
%>Thanks,
%>[email protected]
Max
[email protected]
