Doug, I have had the same "discussion" with both the designers and the board layout guy. Turns out that our standard proctice is to punch holes for each connector pin. The holes are usually 0.100" on the surface layer and 0.130" on the inner layers. The result is overlapping holes that end up leaving a large hole in the inner layer. The edge of this large hole usually looks serrated due to the not completely overlapping holes. Obviously this look will change depending what powers, grounds, signals are connected on any given level.
We have had occaision to go back and modify this approach. This usually happens when the designer finds a performance issue during development or when I have a compliance problem. In that case we have modified the specific connector location, sometimes having to create new pcb layout library components to make this happen. But that is the exception rather than the rule. We also use other means to address this issue. Any signal to a connector over 10 MHz usually gets a dedicated connector or a coaxial type. Any signal from 2 to 10 MHz gets board routing and etch shielding treatments and sometimes filtering. Anything less than 2 MHz gets nothing except as required. Regards, Scott Douglas Principal Compliance Engineer ECRM Incorporated Telephone: 1-508-851-0207 Facsimilie: 1-508-851-7016 e-mail: [email protected] ________________________ _______________________________________________________________________________ From: Doug McKean on Thu, Sep 25, 1997 12:33 AM Subject: EMC Design Question for a Backplane ... To: IEEE Product Safety Technical Committee - I'm having a lively discussion with one of our design engineers about backplane PCB design. Here's the case: 1. Multilayer board, let's say 10 layers, 1 power plane (+5vdc), 3 ground planes, 6 signal planes. 2. Outside world connections to the backplane with several connectors across the back of the product. 3. T1/DS1 product. I want the +5vdc power plane cutaway, actually well away, from pins of the connectors that do not use the power plane. I can't draw it very well with ASCII. But needless to say, if there's a 6-pin connector with 1 pin using the 5 vdc, then I want the 5 volt plane cut away from the other 5 pins with *one* hole. Instead, what's being suggested is to punch *five* separate holes through the power plane like a sieve for each pin not using the 5 volts. My concern is noise, transients, or ESD coupling from the outside world lines to the power plane of the backplane and thus to everything connected to the backplane. Am I being too picky here? What's the standard convention that people use out there? ------------------ RFC822 Header Follows ------------------ Received: by macgtwy.ecrm.com with SMTP;25 Sep 1997 00:33:05 -0400 Received: by highlight.ecrm.com (AA08732); Thu, 25 Sep 97 00:20:16 EDT Received: from ruebert.ieee.org by maildrop.ecrm.com (AAA09548); Thu, 25 Sep 1997 00:20:45 -0400 (EDT) Received: (from daemon@localhost) by ruebert.ieee.org (8.7.5/8.7.3) id SAA26766 for emc-pstc-list; Wed, 24 Sep 1997 18:24:42 -0400 (EDT) From: [email protected] (Doug McKean) To: "IEEE Product Safety Technical Committee -" <[email protected]> Subject: EMC Design Question for a Backplane ... List-Post: [email protected] Date: Wed, 24 Sep 1997 18:16:16 -0400 X-Msmail-Priority: Normal X-Priority: 3 X-Mailer: Microsoft Internet Mail 4.70.1161 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-Id: <[email protected]> Sender: [email protected] Precedence: bulk Reply-To: [email protected] (Doug McKean) X-Resent-To: Multiple Recipients <[email protected]> X-Listname: emc-pstc X-Info: Help requests to [email protected] X-Info: [Un]Subscribe requests to [email protected] X-Moderator-Address: [email protected]
