Punch like a sieve i.e. one hole for each pin insted of a large cut-out. That reduces the inductance of the power/ground plane. The increased noise coupling in insignificant compared to the lost benefits of the low plane inductance. Besides, you reduce the current flow capacity and create current crowding conditions which under certain condition can cause significant EMI radiation. Hans
______________________________ Reply Separator _________________________________ Subject: EMC Design Question for a Backplane ... Author: Non-HP-dmckean ([email protected]) at HP-ColSprings,mimegw5 List-Post: [email protected] Date: 9/24/97 3:16 PM I'm having a lively discussion with one of our design engineers about backplane PCB design. Here's the case: 1. Multilayer board, let's say 10 layers, 1 power plane (+5vdc), 3 ground planes, 6 signal planes. 2. Outside world connections to the backplane with several connectors across the back of the product. 3. T1/DS1 product. I want the +5vdc power plane cutaway, actually well away, from pins of the connectors that do not use the power plane. I can't draw it very well with ASCII. But needless to say, if there's a 6-pin connector with 1 pin using the 5 vdc, then I want the 5 volt plane cut away from the other 5 pins with *one* hole. Instead, what's being suggested is to punch *five* separate holes through the power plane like a sieve for each pin not using the 5 volts. My concern is noise, transients, or ESD coupling from the outside world lines to the power plane of the backplane and thus to everything connected to the backplane. Am I being too picky here? What's the standard convention that people use out there?
