Posted for: [email protected]
> -----Original Message----- > From: [email protected] [SMTP:[email protected]] > Sent: Thursday, November 18, 1999 7:56 AM > To: Rains,Mike > Cc: '[email protected]' > Subject: Re: Printed Wiring Board Design for Safety Compliance > > > > Mike, > > We design analog modems which require basic insulation from selv and TNV3 > (telco). Typically, we place a 2.5 mm wide keep out in our PCB design (in > all > layers) to ensure creepage and clearance distances are met. > > We use Allegro for PCB design and Viewlogic for schematic capture. In > both > tools there exists the option to define properties of components and > nets to define which parts and nets should be isolated . These properties > would > be entered in Viewlogic and imported into Allegro. > > During PCB layout, we utilize Allegro to evaluate routing for EMC > concerns. > > Regards, > > Wolf Josenhans > > > > > > > "Rains,Mike" <[email protected]> on 11/17/99 02:20:33 PM > > Please respond to "Rains,Mike" <[email protected]> > > Sent by: "Rains,Mike" <[email protected]> > > > To: "'emc-pstc @ieee.org'" <[email protected]> > cc: (Wolfgang Josenhans/MW/US/3Com) > Subject: Printed Wiring Board Design for Safety Compliance > > > > > > Colleagues, > > I am curious to know how you handle PWB design for safety compliance: > > 1. How do you document the required spacings on the schematics? > 2. Do you use tools provided by your schematic entry system (ViewLogic, > Valid or whatever) to enter these requirements? > 3. Does your PWB layout system import these requirements from your > schematic entry system and automatically ensure they are maintained as the > board is designed? > 4. How do you view the different circuit "segments" once the board is > designed? That is, how do you visually verify that spacings are maintained > between all "segments" on a single layer and through multiple layers? > > The reason that I'm asking is that this is an area of interest here. Our > boards are typically six layer, very densely populated and can have ac > mains, SELV and intrinsically safe circuit segments. We are developing > ways > to try and reduce human error and effort in designing these boards. I > would > be interested to know if anyone else has an interest in this subject. > Thanks. > > Best regards, > Mike Rains > Foxboro Co. > > --------- > This message is coming from the emc-pstc discussion list. > To cancel your subscription, send mail to [email protected] > with the single line: "unsubscribe emc-pstc" (without the > quotes). For help, send mail to [email protected], > [email protected], [email protected], or > [email protected] (the list administrators). > > > > > --------- This message is coming from the emc-pstc discussion list. To cancel your subscription, send mail to [email protected] with the single line: "unsubscribe emc-pstc" (without the quotes). For help, send mail to [email protected], [email protected], [email protected], or [email protected] (the list administrators).
