Good question.
Have you posted to sci.electronics.cad group to see what their
answers were?
- Robert -
-----Original Message-----
From: Rains,Mike <[email protected]>
To: '[email protected]' <[email protected]>
List-Post: [email protected]
Date: Wednesday, November 17, 1999 2:07 PM
Subject: Printed Wiring Board Design for Safety Compliance
>
>Colleagues,
>
>I am curious to know how you handle PWB design for safety compliance:
>
>1. How do you document the required spacings on the schematics?
>2. Do you use tools provided by your schematic entry system (ViewLogic,
>Valid or whatever) to enter these requirements?
>3. Does your PWB layout system import these requirements from your
>schematic entry system and automatically ensure they are maintained as the
>board is designed?
>4. How do you view the different circuit "segments" once the board is
>designed? That is, how do you visually verify that spacings are maintained
>between all "segments" on a single layer and through multiple layers?
>
>The reason that I'm asking is that this is an area of interest here. Our
>boards are typically six layer, very densely populated and can have ac
>mains, SELV and intrinsically safe circuit segments. We are developing ways
>to try and reduce human error and effort in designing these boards. I would
>be interested to know if anyone else has an interest in this subject.
>Thanks.
>
>Best regards,
>Mike Rains
>Foxboro Co.
>
---------
This message is coming from the emc-pstc discussion list.
To cancel your subscription, send mail to [email protected]
with the single line: "unsubscribe emc-pstc" (without the
quotes). For help, send mail to [email protected],
[email protected], [email protected], or
[email protected] (the list administrators).
