At 09:30 AM 3/3/99 -0800, Allen Tudor wrote: >Clause 5.4.4 of UL 1950, Third Edition specifies that in lieu of creepage and clearance distance requirements for operational insulation, the electric strength test for operational insulation (Table 18) can be used. > >Does anyone know how to calculate minimum distances between traces on a printed circuit board that would allow one to pass the dielectric test at a given voltage? Or has anyone taken any empirical data that would shed light on this topic? Also, would trace width have an impact on the dielectric test results?
This is highly empirical and best done with a hi-pot tester and some bare boards. You're talking about Paschen's Law. Paschen's Law: Breakdown Voltage (BV) for uniform gaps V(kV)= 24.2Sh +6.1(Sh)^0.5 where V is the breakdown voltage in KV S=(293p)/760T h is electrode spacing in cm. p is pressure mm of mercury T is temperature in degrees Kelvin At STP, S = 1 so 30KV/cm is pretty good This relationship does not work for all values of pressure. This is all greatly dependent upon the geometry of the two test points of concern. I believe Paschen came up with this empirical equation with point probes. I like to remember that 3M volts for 1 meter at STP (roughly). That still works with the above equation. But remember that the field about two *point charges* varies inversely with the square of the distance. The field about two *line charges* varies inversely only with distance. So be careful fudging distances with traces. If we have 3MV @ 1m, then 3KV @ 1 mm which is roughly 40 mils. Double it for a x2 safety factor to 2 mm or 80 mils. For reinforced insulation, it's a x2 yet again so that now you have a 4 mm or 160 mil separation. Pick the safety factor that you want. I'm just suggesting this. I seem to remember something about wire mfrs build in a safety factor of x7 into the insulation, but I'm not sure about that. Now, take a look at UL-1950, Table 3, "Minimum Clearances for insulation i primary circuits, and between primary and secondary circuits ..." In the column for >150V, <= 300V with a transient of 2.5KV, you get a rough idea (agreed very rough idea) of how these numbers work out ... " Vrms = 300V, Op = 1.7, B/S = 2.0, R = 4.0 " Some of those clearance numbers look familiar when compared to working it out long hand in my paragraph above? You can bet they do. The trace width does not have an impact on dielectric testing if you're talking about two traces horizontally adjacent on the same layer of the board. Traces vertically adjacent to each other will be a different story since the old standby FR-4 with a Dk = 4.7 will increase the BV by a factor of roughly 4.7. But, again, do your own empirical evaluations on your own boards. It will prove to be invaluable information. Hi-pot testing is one of the most common areas of safety testing failure. --------- This message is coming from the emc-pstc discussion list. To cancel your subscription, send mail to [email protected] with the single line: "unsubscribe emc-pstc" (without the quotes). For help, send mail to [email protected], [email protected], [email protected], or [email protected] (the list administrators).
