Clause 5.4.4 of UL1950, Third Edition specifies that in lieu of creepage and clearance distance requirements for operational insulation, the electric strength test for operational insulation (Table 18) can be used.
Does anyone know how to calculate minimum distances between traces on a printed circuit board that would allow one to pass the dielectric test at a given voltage? Or has anyone taken any empirical data that would shed light on this topic? Also, would trace width have an impact on the dielectric test results? Allen Tudor, Compliance Engineer PairGain Technologies tel: (919)875-3382 2431-153 Spring Forest Rd. fax: (919)876-1817 Raleigh, NC 27615 email: [email protected] Allen Tudor, Compliance Engineer PairGain Technologies tel: (919)875-3382 2431-153 Spring Forest Rd. fax: (919)876-1817 Raleigh, NC 27615 email: [email protected] --------- This message is coming from the emc-pstc discussion list. To cancel your subscription, send mail to [email protected] with the single line: "unsubscribe emc-pstc" (without the quotes). For help, send mail to [email protected], [email protected], [email protected], or [email protected] (the list administrators).
