Hi, My question concerns providing ESD protection to analog circuitry on a card. Currently, I have a common ground for the entire card (2S2P). For reasons, the card has to be tied to chassis. ESD discharge (air or contact) to the chassis causes ground level to move up, thus reducing noise margin and causing circuit malfunctioning. The ASIC chip in question has both analog and digital circuits, with separate decoupling capacitors for analog and digital power.
Connecting a small (120 pF) capacitor directly across the analog power and ground pins seems to provide some improvement in the ESD immunity. We are considering a board redesign. Will it help if the ground plane below the ASIC is sectioned to provide a separate analog ground, connected to main ground at one location only near the decoupling capacitors, perhaps through a small inductor. Will this introduce other problems. Any other ideas !!!!! Regards, Ravinder PCB Development and Design Department IBM Corporation Email: [email protected] *************************************************************************** Always do right. This will gratify some people and astonish the rest. .... Mark Twain ------------------------------------------- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: [email protected] with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Michael Garretson: [email protected] Dave Heald [email protected] For policy questions, send mail to: Richard Nute: [email protected] Jim Bacher: [email protected] All emc-pstc postings are archived and searchable on the web at: http://www.rcic.com/ click on "Virtual Conference Hall,"
