Dear all,
Are you working with a MLB, if so how many layers and what is your stack
assignment? I think if you are looking for a rule of thumb on layout
density, you can end up literally barking up the wrong tree.
I believe the correct rule of thumb is not to let a critical trace/track
cross any of the ground/power layer. This Swiss cheese phenomena (presence
of holes and gaps in the ground/power plane) result in large loop areas for
the return current ( inductance) because the ground (return current
'image') plane was full of obstructions and obstacles. I assume that you
are working with a 4 layer board, you could try to place the 'signal layer'
over the ' ground /power' planes and see if the critical tracks/traces does
cross any ground gaps. First check if the ground and power plane are all
gapped in the same places.
:-)
best regards
Tim Foo
Ken Javor
<ken.javor@emccomplian To:
[email protected]
ce.com> cc: (bcc: Wan Juang
Foo/ece/staff/npnet)
Sent by: Subject: PCB layout
question for good EMC performance
owner-emc-pstc@majordo
mo.ieee.org
06/08/02 04:19 AM
Please respond to Ken
Javor
I have a problem where a very large number of chips are mounted on a very
small board. The ground plane looks like Swiss cheese and there is ground
bounce accordingly. For future reference, is there a rule-of-thumb for how
much PCB area should be allocated per number of IC chips/pins so as to be
able to provide ground returns for all important signal/clock routing?
<snip>
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