I investigated the phenomenon of capacitor damage by transients and found 
caps to be very resistant to damage from short duration, especially high
source impedance (50 Ohm) spikes.  There is a complete write up entitled,
"Investigation Into the Effects of Microsecond Power Line Transients on
Line-Connected Capacitors" NASA/CR-2000-209906 at:

http://see.msfc.nasa.gov/

As I write this, I cannot access the site and get you the precise page it is
on, but it is usually accessible to the public (a pdf download).  I also
have the original in MS Word that I can send if necessary.



----------
>From: Chris Chileshe <chris.chile...@ultronics.com>
>To: "'EMC-PSTC List'" <emc-p...@majordomo.ieee.org>
>Subject: Baffled by EFT test results (EN61000-4-4)
>Date: Fri, Oct 25, 2002, 6:55 AM
>

>
> Hi Group,
>
> So I went ahead and built a test PCB with my inductors and ferrites in PI
> filter formation with capacitors - just like I threatened to do a few months
> ago ( e-mail subject header "Designing for low power radiated and conducted
> immunity" describing a small 3-wire low power DC pressure sensor).
>
> The analog circuit simulating a pressure sensor is simply a 5V regulator
> (LP2985) supplying a AD623 IN-amp monitoring the differential voltage across a
> wheatstone bridge (4k7) connected to the same 5V rail. The output then
> simply connects to an Avometer (through a PI filter of course). A variant of
the
> test PCB doesn't even have the regulator. It is that simple.
>
> I took the PCB through radiated immunity testing to EN 61000-4-3 and met
> 100V/m, and through conducted immunity testing to EN 61000-4-6 and met
> the 10V level.  All tests were done with unscreened cable. I also proved the
> protected circuit was susceptible when the filter was removed.
>
> Having decided I had sized my inductors, ferrites and caps appropriately,
> and done the PCB layout correctly, I then proceeded to add small SMT varistors
> for transients to EN 61000-4-4. The test PCB was again good for 2kV. I
> then shuffled the relative positions of the varistors in the circuit
> (initially pre-
> PI filter, then post PI filter ) and it didn't seem to make any difference.
The
> idea was to get some permutations of varistor location and then repeat the
> RF immunity tests in case the varistors introduced susceptibility (an
> observation I have made in the past).
>
> I then took the varistors off the board altogether and still the PCB meets the
> 2kV stress levels ( I am using the levels of EN 61000-6-2 ). I am not
> too keen to raise the stakes to 4kV just now because there are more tests
> I would like to perform on the PCB before I let it go up in smoke.
>
> This is probably the first time I have seen anything get through transients
> testing without any explicit measures to mitigate against failure. Has anyone
> experienced this? Is there an explanation for this?
>
> I have always used varistors almost as a matter of course, so you can
understand
> my surprise.
>
> Could it be I have "over-designed" my RF filter to the point it is good
> enough for the EFTs as well? The caps are only rated for 50V though ( the
clamping
>  voltages of the varistors).
>
> Could it be the caps are in fact rated for such transients although this may
not
> be stated explicitly? Should I prolong the exposure of the varistor-free
> circuit at
> 2kV to see if I am dealing with "delayed failure" potentially? I have been
setting
> my burst duration to 1 minute.
>
> Any pointers?
>
> Regards
>
> - Chris Chileshe
> - Ultronics Ltd
>
>
>
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