All, I'm trying to convince a few people here that completely separating the digital and chassis grounding on our product is not always the best way to go. Unfortunately, a lot of the people I'm dealing with are ex Bellcore engineers who worked a lot with isolated grounds and are convinced that isolated grounds are the only way to go. Now we're dealing with optical interfaces and speeds well in excess of 100MHz, so I really want to see the grounds tied together as much as possible.
While I know that combining the digital and chassis grounds is for the most part better once you get above a few hundred MHz, putting together concrete arguments is proving to be a bit elusive. I luckily have some high level backing that will let me push my views, but I am one person up against a team of industry vets. If anyone has been in this boat before and won, could you share some of the tactics or arguments that you used? I know this issue has been discussed in the past, but a fresh discussion of the relative benefits of isolating the D and Cgnds would probably be beneficial to the group as well. See below for my views on the issue. Thanks!!!! Dave My views for telecom equipment with a backplane and plug in circuit packs (and a good tight chassis around it all): (Note that Analog grounds are outside of the scope of this statement - I'm focusing on Digital grounds and Chassis ground) The benefits of separating Dgnd and Cgnd have to do with defining your signal impedances and SI in general. When you place this system inside a Cgnd "balloon", all should be well but maybe there is some extra noise due to RF being trapped within the balloon. However, if the Cgnd and Dgnd are tied together throughout the system, the effect should be similar to "heat shrinking" your conductive chassis Cgnd ballon onto your Dgnd. The single ended signal return currents should still follow their original paths and things should essentially remain unchanged. I could see some possibility (I'll avoid use of the word potential here :o) ) for RF currents on the circuit pack card grounds due to RF fields contained within the faraday cage, but I think these could be mitigated by clever bonding of the grounds on circuit packs. I think that isolating the faceplate from the Dgnd on the circuit packs but stitching the bottom edge (faceplate to backplane) Cgnd ESD guard band to Dgnd could alleviate stray currents on the cards and keep them relatively clean - all while still maintaining the bonding of the Cgnd and Dgnd on a system level. The idea (as my brain developed it) is to keep the stray currents at the periphery of the card by limiting the through connections on the circuit packs and forcing stray currents to flow near the edge of the card. The backplane should for the most part have Dgnd and Cgnd be one and the same. Does this raise any red flags for anyone? I'm expecting at least a few, but this is the best scheme that I can come up with right now. ------------------------------------------- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: [email protected] with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: [email protected] Dave Heald: [email protected] For policy questions, send mail to: Richard Nute: [email protected] Jim Bacher: [email protected] All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on "browse" and then "emc-pstc mailing list"
