Hi all, A couple of weeks ago, I started a thread trying to relate creepage and clearance distances on the surface of a circuitboard to layer spacing of interior layers of a circuitboard. I deal with EN 61010-1; and I'm considering "double insulation" between AC and SELV.
The result of that thread was that creepage and clearance is a "surface" issue. Once inside the board, I should look at the minimum "through insulation" distances as a guideline. A distance of 0.4mm from EN 60950 was mentioned. Well, we had our board laid out. We put 0.018" between hazardous voltages and SELV. We applied this distance to traces on the same layer and to the interlayer insulation distance. When it came to interlayer insulation, we needed this gap in three places (between four layers of the board). The board is eight layers and has a total thickness of 0.093". Once you do the math and add in the thickness of two ounce copper, this left us about .004" for other layers. So, starting from the component side, we had interlayer insulation thicknesses of 0.018", 0.018", 0.018", 0.004", 0.004", 0.004", 0.004". When we went for prototypes, the board house laughed us out of the building. Their feeling was that this board would warp like a potato chip. The thicker insulation layers on the component side would heat much more slowly than the thin layers on the solder side. ************************ This is where it gets sticky***************************** I seem to remember reading an EMC-PSTC thread regarding this minimum thickness saying that the reason behind it was to prevent arcing through pinholes in the insulation. I seem to remember that thread continuing to say that it is alright to use thinner insulation, as long as there are multiple layers of it; and as long as each layer had enough dielectric strength. The reasoning behind this is that pinholes in the insulation layers wouldn't line up; and there would be an infinitesimal probability of there being a "pinhole" path all of the way through three layers. If there was a pinhole in one layer, there would still be enough dielectric strength in the other layers to prevent arcing. I then combined this with the fact that FR4 has a rating of at least 1200 Volts/mil. This would tell me that I could "stack" multiple layers of .002" FR4 and have a "safe" design with about three layers. I also learned that most circuitboard conductive layers are separated by multiple insulation layers of stock sizes such as "106", "1080", 2113"... I had to ask the guy at Nelco to explain the jargon to me :-) He also informed me that stacking too many of these fiberglass sheets together would lead to possible degradation of registration. So, I have directed the board house to look at reducing the .018" spaces to .010"; but, they need to make sure that this .010" has at least three layers of fiberglass (such as 1 layer of "106" (2 mils thick) and 2 layers of "2113" (4 mils thick)) within it. I then had them divide the saved thickness among the other layers in order to even things out a bit. Can anyone see any "pinholes" in my reasoning? Can anyone recall the thread regarding multiple layers of thin insulation? Chris Maxwell | Design Engineer - Optical Division email chris.maxw...@nettest.com | dir +1 315 266 5128 | fax +1 315 797 8024 NetTest | 6 Rhoads Drive, Utica, NY 13502 | USA web www.nettest.com | tel +1 315 797 4449 | ------------------------------------------- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on "browse" and then "emc-pstc mailing list"
