If this is what you feel in necessary at moderate frequencies (I believe the original discussion was related to 600 MHz), I'd hate to see what you might feel is required at high frequency. :)
The idea of "chip in board" that you mention is not new. It was first tried in the Far East some years ago as a means of allowing closer component packing. So far, it has been shown to be impractical. Bob Wilson TIR Systems Ltd. Vancouver. -----Original Message----- From: Wan Juang Foo [mailto:[email protected]] Sent: April 3, 2002 5:54 PM To: Cortland Richmond; ieee pstc list Subject: Re: EMC & SIX LAYER PCB Assuming we are referring to small SMD components. The voltage drop across a capacitor, (in this instance I take it that you meant the bypass capacitor) is a function of the gap between the vias from the power and ground planes. Here is another little trick, but it is subjected to having the manufacturing and assembly people cooperating on this issue of board performance. I must caution that this stage of development in general, manufacturing do not allow placing a pair of closely spaced via (pwr & gnd) right under a cap. In ASCII art the plan view of the pad and via combo looks like this. []:[] This however would push the typical resonance by a few octave over the conventional layout and it is dependent on the thickness of the board. The next step in the development is to boast the ability of the buried capacitance by inserting a 0603(1.6x0.8x0.8 mm) sized capacitor vertically into a hole on the PCB and solder the top and bottom ends. This have been found to fit well in the standard 1.6 mm thick board. The hole can have partial plate through. Again in ASCII art the elevation view looks something like this. ] C [ A ===== pwr and ground layer ] P [ I can not wait to drive all the PCB shopfloor and assembly people up the wall every time I come up with an innovation. cheers Tim Foo Cortland Richmond <72146.373@compuserve. To: John Coyle <[email protected]>, ieee pstc list <[email protected]> com> cc: (bcc: Wan Juang Foo/ece/staff/npnet) Sent by: Subject: Re: EMC & SIX LAYER PCB owner-emc-pstc@majordo mo.ieee.org 04/04/02 01:35 AM Please respond to Cortland Richmond A good thread. Some additional thoughts. This is a favorite question of interviewers hiring EMC engineers (any reading?): "How would you stack this board?" Looking at the problem as controlling impedance, things fall into place. Impedance to signal returns is impedance to signals. One SHOULD avoid switching reference planes. But the effect of switching reference planes is reduced if the potential required to pass return current between them - impedance, including between sides of the SAME plane - is minimized, which is where nearby "ground" via's and bypass capacitors come in. Current flowing through a via or a capacitor creates a voltage drop which drives the planes it connects, as a radiator. A good antenna may be made out of planes connected by a via, with RF applied between them. We need to avoid doing this by _accident_! The return path for a trace penetrating a reference layer should be as close as possible to the penetrating signal. While having it further off does not change the via's impedance, it does require current flowing through it to go further and increases the size of the radiating and coupling loop. This is also an impedance inserted in series with the desired signal. A bypass capacitor is is not only a path for return currents, but a place where cross talk can occur; it is a common impedance for all currents which flow through it, and voltage across it is in series with signals whose currents pass through it. If it is used to pass signal return currents, it needs to be sized not only for the current demand of devices its storage supplies, but also for the edge rate of signals whose return currents pass through it. If it is operated above self-resonance, it _may_ form a parallel resonant circuit with parasitic capacitance (or other capacitors), and add unexpected impedance to the signal return. At the right (wrong) place this can do a good impersonation of the feed to a patch antenna. It is common now to use a pair of planes, power and ground, sometimes on a very thin layer (AKA "buried capacitance") to minimize power supply impedance. Unless this pair is rather extensive, it will need to be augmented by discrete bypass capacitors, which should not have long via's connecting them. This means near the surface. Signal traces need to be near planes for high-frequency return currents. BGA technology requires micro-via's between devices and surface or deeper planes. In addition, building boards, we seem to prefer pretty much constant trace width and spacing even while controlling impedance, and this means interior traces need to be further away from planes for the same impedance at a given width. (Differential traces really should be coupled much more to each other than to nearby planes, though often this is ignored. Providentially, yesterday's mailbox brought the IEEE Transactions on Electromagnetic Compatibility, volume 44, which includes on page 11 an analysis of what I've been yelling at engineers for years. Heh! See: _The Impact of a Nonideal Return Path on Differential Signal Integrity_, Per Fornberg, Mark Kanda, Christopher Lasek, Melinda Piket-May and Stephan H. Hall.) Adding all the above, I come up with something like 1. TRACE R : route slower nets and break out BGA's THIN : lower impedance of surface traces 2. POWER : return paths for upper layer THIN : semi-"buried capacitance" 3. GROUND : Bulk caps are on top. NORMAL : raise impedance to next trace layer 4. TRACE : high speed, between planes NORMAL : raise impedance to adjacent traces 5. GROUND : return for high frequency currents on adjacent and surface layer THIN : lower impedance for surface layer 6. TRACE : surface layer This does somewhat violate copper symmetry about the core, and may cause complaints from the fab shop. It CAN be done. It will also cause headaches in routing on a dense board, as it allows only three dedicated trace layers. Portions of the ground and power planes may be used for routing. They will be anyway, right? Just control impedance and coupling. The issue of which goes next to the surface, ground or power, is an open one. Consider impedance when you decide. Some people like ground layers on the surface. REALLY high speed boards may need this. But it gives the board fab shops screaming fits and hurts yield. At only 66 Mhz, you should not have to need to do that. Cheers, Cortland ------------------------------------------- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. 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