I will send a list of three good books on these two connected subjects (signal
integrity and PCB EMC) in a day or two. Basically and briefly here is my
viewpoint:

For signal integrity you must be familiar with transmission lines; how to
visualize signal propagation along a T-line and how to perform simple
simulations. I use the free evaluation version of MicroCap-7 for T-line
simulation. This really helps in predicting what will happen or to explain
what strange things you are seeing in your PCB. So, think like an
electromagnetic wave. Maintain a constant impedance through the signal path.
Terminate either the source, the load, or both ends of the T-line if the path
is >1/6 the signal rise time. And most importantly, use a power plane and a
GND plane. This means a minimum of 4 layers. If you are doing low-cost
consumer designs you will be pressured to minimize the number of layers. This
is where an experienced signal integrity engineer can save you money. 

For PCB EMC don't design the PCB to be an antenna. You might want to study
antennas. Think of monopole antennas (daughter cards) and loop antennas (PCB
traces and IC lead frames). Minimize the height of daughter cards and
components. These radiate by common mode current. Minimize the loop area of
the loop "antennas". These radiate by differential mode current. Use PCB's
with a power and a GND plane. This means at least 4 layers. Don't split planes
unless you understand what the implications are. These form slot antennas and
signal integrity problems if there is RF current trying to flow across the
slot.

Bringing DUT cables out of an enclosure is a great way to fail EMI tests. It
takes only about 1 mV of RF on a 1/4 wavelength DUT cable to fail EMI tests.
Any DUT cables that are shielded need the shield to be 360-degree terminated
to the conductive enclosure. This ensures that the cable and enclosure have
zero RF potential between them. No RF potential means no RF current on the
"antenna". 

   Dave Cuthbert
   Micron Technology


From: Cortland Richmond [mailto:[email protected]]
Sent: Friday, April 25, 2003 5:18 PM
To: [email protected]; ieee pstc list
Subject: Re: Check list for PCB Layout



>> I would like to create a check list in order to help designers and PCB
routers of my company to improve their design / EMI and SI. <<

This is one of the things we get paid to do, assuming anyone is
paying us at all. For this and other reasons given by those who've
already answered your request, it is something you will usually have
to come up with on your own, or pay someone to give you. This last
can often be done by paying them to give your board designers a
seminar on signal integrity; the printed materials supplied with
the course almost always have some kind of check list included, or
at least, rules you can make into one.

Luckily, it's not hard to come up with a check list that will make
a difference in your boards. In its simplest form, it can be nothing
more than a list of everything done _wrong_ over the past few years,
with "Do not ..." in front of it. 

For example,
"Do not "
interrupt ground planes.
delete return traces.
leave out ground vias when changing layers.
run high speed clocks on board edges.
share ground traces and connector pins between critical signals.

and so on.

The physics is fairly direct. Getting your check list implemented, that
can be difficult, and I've often thought a seminar on the "politics" of
EMC would be as valuable as one on its physics.

Good luck!


Cortland


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