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Chris, I wrote some time an application note for our customers. (attached). Maybe it helps you. Horst INNOVA Product Service GmbH Ampferweg 6 87677 Stöttwang Tel: 08345-952727 Fax : 08345-952729
Von: [email protected] mailto:[email protected]]Im Auftrag von Chris Wells Gesendet: Freitag, 5. März 2004 04:41 An: EMC-PSTC Discussion Group Betreff: Inner PCB spacing UL61010A-1 ground plane to via. >From what I can see, UL61010A-1 does not have direct specifications for inner board spacings. Am I missing something - are there guidelines? Section 6.7 basically falls back on surviving the voltage tests..... All the same there has to be some practical guide on how close to allow inner board spacing. I do not worry so much layer to layer but it is the vias that drill down through a ground plane that concern me. That is where the imperfections may show up I figure. If the via circuit is hazardous and requires high pot testing relative to ground plane - how close can the ground plane get to the via? One of my coworkers takes the Basic C&C spacing used for the circuit on the surface of the PCB and divides it in half and uses that value with good results. Thanks Chris Wells
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Chris, I wrote some time an application
note for our customers. (attached). Maybe it helps you. Horst INNOVA Product Service GmbH Ampferweg 6 87677 Stöttwang Tel: 08345-952727 Fax : 08345-952729 -----Ursprüngliche
Nachricht----- From what I can see, UL61010A-1 does not
have direct specifications for inner board spacings. Am I missing something - are there
guidelines? Section 6.7 basically falls back on
surviving the voltage tests..... All the same there has to be some
practical guide on how close to allow inner board spacing. I do not worry so much layer to layer but
it is the vias that drill down through a ground plane that concern me. That is where the imperfections may show
up I figure. If the via circuit is hazardous and
requires high pot testing relative to ground plane - how close can the
ground plane get to the via? One of my coworkers takes the Basic
C&C spacing used for the circuit on the surface of the PCB and divides it
in half and uses that value with good results. Thanks Chris
Wells |
APP_PLANAR_TRANSFORMATOR_IEC60950-2.pdf
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