I am not sure if this is belated or not, but if I could give an advice in the simplest form on how to select the PCB stackup, I would recommend always trying to acheive these two things: 1) Kepp Vcc and GND layers closely spaced. Nowadays the PCB vendors can use 2 or 3 mils FR4 as standard material. 2) Place routing (signal) layers adjacent to GND planes rather than Vcc planes. Avoid by all means placing signal layers between Vcc and GND layers. Following these two advices makes it significantly easier to do right things, and avoid obstacles, later during the layout. Enything else is trading off performance for something, usually price - so remember it and make a judgment about whether you can afford it (often you can). Good luck, Neven
-------------- Original message -------------- John - consider this resource on board stack up http://www.hottconsultants.com/ And specifically http://www.hottconsultants.com/tips.html - see PCB stack up. This was a great help to me as were several members of our group. BTW - my project I talked about ~ a year ago is nearing production and on my Alpha boards I achieved Class B emissions and high noise immunity. For example I passed EN61000-4-3 at 35V/M with 80% 1KHz AM mod. This is to coordinate with ANSI C37.90.2 and insure some head room. I have both 8 and 10 layer boards. The 10 layer board has DSP running at 133MHz and powered at 3.3 and 1.8V. If you remember I had an odd split analog arrangement and that has turned out to behave as well despite the digital noise making right in the middle. Thanks to all that gave me guidance! Right now I am receiving some Beta boards (set prior to production build) and I hope we did not step on anything. I am curious if any have experience with the high capacitance boards which increase the dielectric constant between power and ground by adding ceramic material to the prepreg? This is referred to as "Buried Capacitance" See http://www.sanmina-sci.com/Solutions/pdfs/Licensee_List.pdf See bottom of note http://www.hottconsultants.com/techtips/decoupling.html I believe you need to have ground planes that cover entire board and I have isolated sections so I suspect it would not work. As I undertand it there are some mechanical warping issues with out a continous ground plane over the entire board. I was thinking this technology could give me a way out if Lab Validation testing does not cofirm my prescreening. Also I have not studied how this technology effects the trace/PCB characteristic impedance. Presently my boards are designed to 50 ohms and the peripheral busses run at 133 MHz. This is the highest speed board I have worked with and am blazing new territory for our embedded designs. Lastly - My design has 5 BGAs on the 10 layer board and I asume this type of PCB would effect the thermal profile. Is it hard to adjust to? Chris Wells - Fellow Engineer, Eaton Electric [email protected] ----- Original Message ----- From: [email protected] To: [email protected] Sent: Wednesday, December 08, 2004 5:37 PM Subject: Design for emc and pcb stack-ups Hello, I am embarking on an electronic design for a cctv camera that will employ 8 or 10 layer PCB. It will include a high speed DSP (400-600MHz internal clock) that requires both 3V3 and 1V2 supplies I am considering employing dual power planes rather than segment a single power plane. I would appreciate any feedback on... reference material that outlines pros/cons of either solution single or dual plane. Material describing stack options for optimum emc - 8 or 10 layer? Most of the references I have reviewed do not directly address dual power layers in the stack. Any comments appreciated. Thanks John Coyle Senior Engineer Video Systems 6554 - 176th Street Surrey, BC Canada V3S 4G5 _____ Honeywell 604.574.1526 x8633 ! ; [email protected] 604.574.8523 Fax ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. Website: http://www.ieee-pses.org/ To post a message to the list, send your e-mail to [email protected] Instructions: http://listserv.ieee.org/listserv/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Ron Pickard: [email protected] Scott Douglas [email protected] For policy questions, send mail to: Richard Nute: [email protected] Jim Bacher: [email protected] All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. Website: http://www.ieee-pses.org/ To post a message to the list, send your e-mail to [email protected] Instructions: http://listserv.ieee.org/listserv/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas [email protected] For policy questions, send mail to: Richard Nute: [email protected] Jim Bacher: [email protected] All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. Website: http://www.ieee-pses.org/ To post a message to the list, send your e-mail to [email protected] Instructions: http://listserv.ieee.org/listserv/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas [email protected] For policy questions, send mail to: Richard Nute: [email protected] Jim Bacher: [email protected] All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc
