John, there are many ways to go. Here are two 8-layer stackups that should work well: TOP (sig + GND flood) GND SIG PWR1 PWR2 SIG GND BOTTOM (sig + GND flood) Spacing between layers can be as small as 6 mils. In this case the top traces (for 50 ohms) will be 10 mils wide. The internal traces are 5 mils wide. The spacing between PWR1 and PWR2 is adjusted to obtain the total board thickness required. The downside of this stackup is fairly high PWR plane impedance because the PWR planes and far from GND. This next stackup has 1/2 the power plane impedance. The downside with this is that the internal SIG layers are referenced to the PWR planes rather than GND and PWR as in the first stackup. TOP (sig + GND flood) GND PWR1 SIG SIG PWR2 GND BOTTOM (sig + GND flood) Spacing between layers can be as small as 6 mils. The spacing between PWR1 and PWR2 is adjusted to obtain the total board thickness required. The downside of this stackup is fairly high PWR plane impedance because the PWR planes and far >from GND. Note that the spacing between the two internal SIG layers is 20 mils to obtain a 63 mil total board thickness (1/2 oz copper). The internal traces are far enough apart to have little cross talk. They need to be 7 mils wide for 50 ohms. Here is a link to a trace impedance calculator: http://www.emclab.umr.edu/pcbtlc/ Dave Cuthbert Micron Technology
From: [email protected] mailto:[email protected]] On Behalf Of [email protected] Sent: Wednesday, December 08, 2004 3:38 PM To: [email protected] Subject: Design for emc and pcb stack-ups Hello, I am embarking on an electronic design for a cctv camera that will employ 8 or 10 layer PCB. It will include a high speed DSP (400-600MHz internal clock) that requires both 3V3 and 1V2 supplies I am considering employing dual power planes rather than segment a single power plane. I would appreciate any feedback on... reference material that outlines pros/cons of either solution single or dual plane. Material describing stack options for optimum emc - 8 or 10 layer? Most of the references I have reviewed do not directly address dual power layers in the stack. Any comments appreciated. Thanks John Coyle Senior Engineer Video Systems 6554 - 176th Street Surrey, BC Canada V3S 4G5 _____ Honeywell 604.574.1526 x8633 [email protected] 604.574.8523 Fax ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. Website: http://www.ieee-pses.org/ To post a message to the list, send your e-mail to [email protected] Instructions: http://listserv.ieee.org/listserv/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Ron Pickard: [email protected] Scott Douglas [email protected] For policy questions, send mail to: Richard Nute: [email protected] Jim Bacher: [email protected] All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. Website: http://www.ieee-pses.org/ To post a message to the list, send your e-mail to [email protected] Instructions: http://listserv.ieee.org/listserv/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Ron Pickard: [email protected] Scott Douglas [email protected] For policy questions, send mail to: Richard Nute: [email protected] Jim Bacher: [email protected] All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc
