Thanks everyone so far for the replies. I cannot use Spread Spectrum (I would if I could) and it looks like I cannot put resistors in the data lines due to other design constrains. I have determined it is the SDRAM because I have a means of keeping the other side of the bus running/forced, including the clock input to the SDRAM, while I shut down the SDRAM (removed ferrite bead from the power supply). Under these conditions, I do not see any appreciable emission at the SDRAM frequencies.
I already looked into slowing the clock line, with no effect to the emission (my feeling is that maybe the data are contributing more than the clock). The power supply is filtered as much as it can be with a combination of ferrite beads and caps. Te clock rooutinig is as good as it gets (i.e. pretty "good"), and the data lines are not perfect - I had no choice. They are all abouot 1.5" long. A lower-power memory is definitely something I will look into, but I have to check various parts (which it seems I will have too do anyways). I know how to run a comparison between various memory modules, but I wondered if anyone has already done it. If I do not succeed in finding something that creates less emission, it seems I will be stuck with a PCB "can" over the SDRAM section, which I would like to avoid (although in the end I may have to use it). It is only about 1-2 dB over B, and I am trying to find a friendly solution, so looking for a quieter SDRAM is one option. I have no problem usinig "brute force" to kill the emission, but it would add cost. Neven -------------- Original message -------------- From: "David Cuthbert" <[email protected]> Neven, If you are using spread spectrum modulation it will help to set the spread to maximum. You can tell if it is the clock or the DQs by seeing if the emissions increase during the exercise program. The 2-layer PCB sounds like an EMC challenge in a plastic enclosure. A single SDRAM package can radiate enough by itself to fail class B near 1 GHz. PCB traces that act as antennas can cause the system to fail at lower frequencies. It does sound like you would like to fix things by changing the SDRAM. The DQ edge shape isn’t very important below 500 MHz (or even higher). Reducing the DQ output current via series resistors (generally 22 ohms) can help a little bit. SDRAM DQ driver crowbar current can be an issue. If it is, output resistors will have no affect. Dave Cuthbert Linear Technology _____ From: [email protected] [mailto:[email protected]] On Behalf Of [email protected] Sent: Friday, February 09, 2007 2:20 PM To: [email protected] Subject: Best SDRAM for Low-Emission? Hello everyone, I have a 2-layer PCB design, plastic enclosure, using 120 MHz SDRAM, two stuffing options: 2MB (16 Mb) in 50-pin tsop package or 8MB (64 Mb) in 52-pin tsop. It is slightly above class B radiated emission at the multiples of 120 MHz. I troubleshot it and I determined the SDRAM is the only source of the failing frequencies, everything else is quiet. I wonder if anyone has looked in how various manufacturers' memory chips perform emission-wise, particularly the type that I am using. I hope to find a manufacturer who makes "quieter" modules, so I do not need to change anything else on my board. If anyone has done such a comparison/investigation, I would appreciate if you would be willing to share, on-line or off-line, the results - which memory/manufacturer works best EMI-wise in such conditions. Regards, Neven - ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. Website: http://www.ieee-pses.org/ To post a message to the list, send your e-mail to [email protected] Instructions: http://listserv.ieee.org/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas [email protected] Mike Cantwell [email protected] For policy questions, send mail to: Jim Bacher: [email protected] David Heald: [email protected] All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc ______________________________________________________________________ This email has been scanned by the MessageLabs Email Security System. For more information please visit http://www.messagelabs.com/email ______________________________________________________________________ - ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. Website: http://www.ieee-pses.org/ To post a message to the list, send your e-mail to [email protected] Instructions: http://listserv.ieee.org/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas [email protected] Mike Cantwell [email protected] For policy questions, send mail to: Jim Bacher: [email protected] David Heald: [email protected] All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc
