My usual caveat - am an EMC amateur. If the transient is propagated in serial 
fashion then 're-emitted' (as theorized by Mr Woodgate) with similar 
characteristics as test pulse, do not see how the typical control loop would 
see the disturbance, other than a resultant OV lock-out. Oscillations on the 
PFC FET could result if the transient energy were coupled to a hi-z gate drive 
circuit, but, at least logically, it would seem that the main controller would 
just lock or skip pulses until the disturbance energy is gone.

Observed this 10 years past during variations of EFT and surge test 
configurations while playing with floating and ground-referenced mains on an 
open-frame SMPS, where the chassis could be ground pin-reference or floated. 
Observed again last year while testing another factory's class II p/s where my 
GRP was not correctly placed.

Response of given model SMPS to ESD/EFT/Surge can vary somewhat, where the 
difference is the end-use installation. EMC testing of an COMPONENT p/s is 
problematic and mfr's test data may not be representative of performance in 
your box. This may become a recurring and noticeable problem as SMPS go to 
higher switching frequencies to increase efficiency and decrease size per 
industry demands.

Perhaps TC108 can consider looking at this for the glorious coming of 
IEC62368-1, as there are power supplies being developed now that operate up to 
30MHz.

Brian

-----Original Message-----
From: CR [mailto:[email protected]] 
Sent: Wednesday, November 05, 2014 7:16 AM
To: [email protected]
Subject: Re: [PSES] New electrical phenomenon reproduced tonight!

I suspect the effect seen with SMPS' is due to transients forcing operation 
outside the designed stability region of their controllers.  
If so, this would not be a new EM effect, but a common immunity problem.

Cortland Richmond

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