See terminology in 47 CFR 15.33, similar stuff in CISPR32. Brian
From: Gary McInturff [mailto:gary.mcintu...@esterline.com] Sent: Thursday, January 28, 2016 11:16 AM To: EMC-PSTC@LISTSERV.IEEE.ORG Subject: [PSES] Highest clock frequency in a device. I was looking through standards I have but can't find an absolute description of highest clock frequency. The overall device has clocks well below 105MHz, the point at which the spectrum above 1 GHZ must be investigated during radiated emissions. However one of the IC's has an internal frequency well above that. My understanding of highest clock would include this IC internal, contained within the chip and not provided to any I/O pins. Others disagree, but I can't find any explicit documentation that defines this. Can anyone pin point a textual definition? Thank you - ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. To post a message to the list, send your e-mail to <emc-p...@ieee.org> All emc-pstc postings are archived and searchable on the web at: http://www.ieee-pses.org/emc-pstc.html Attachments are not permitted but the IEEE PSES Online Communities site at http://product-compliance.oc.ieee.org/ can be used for graphics (in well-used formats), large files, etc. Website: http://www.ieee-pses.org/ Instructions: http://www.ieee-pses.org/list.html (including how to unsubscribe) List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas <sdoug...@ieee.org> Mike Cantwell <mcantw...@ieee.org> For policy questions, send mail to: Jim Bacher: <j.bac...@ieee.org> David Heald: <dhe...@gmail.com>
