Hi Ken,

The biggest problem I see when faced with RE issues is that clocks, 
data/address buses and other fast-edged signals do not have an adjacent solid 
return plane. This is especially important for wireless devices. Have your 
client check their stack-up, because invariably, you’ll find, if four layers 
(top to bottom), s-g-p-s, with the power and ground return way too far 
separated (30 to 40 mils (poor HF decoupling) and with the bottom signal layer 
referenced to power, instead of the return plane.

I discuss this in my four-part article on low EMI design for PC boards: 
https://www.edn.com/design-pcbs-for-emi-part-1-how-signals-move/ 
<https://www.edn.com/design-pcbs-for-emi-part-1-how-signals-move/>

Cheers, Ken

_______________________

I'm here to help you succeed! Feel free to call or email with any questions 
related to EMC or EMI troubleshooting - at no obligation. I'm always happy to 
help!

Kenneth Wyatt
Wyatt Technical Services LLC
56 Aspen Dr.
Woodland Park, CO 80863

Phone: (719) 310-5418

Web Site <http://www.emc-seminars.com/> | Blog <https://design-4-emc.com/>
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> On Jan 26, 2021, at 10:10 AM, Ken Javor <[email protected]> wrote:
> 
> At my request based on this EMC forum back and forth and the specs on the 
> processor which is very slow, customer is going to measure clock waveform.
> 
> Ken Javor
> Phone: (256) 650-5261
> 
> 
> From: "Grasso, Charles" <[email protected] 
> <x-msg://20/[email protected]>>
> Date: Tue, 26 Jan 2021 16:19:30 +0000
> To: "[email protected] <x-msg://20/[email protected]>" 
> <[email protected] <x-msg://20/[email protected]>>, Ken 
> Javor <[email protected] <x-msg://20/[email protected]>>
> Subject: Re: [PSES] Digital logic question
> 
> ​Agreed.  Perhaps your customer could take a measurement on the pwa?
> From: Ken Javor <[email protected] 
> <x-msg://20/[email protected]>>
> Sent: Monday, January 25, 2021 12:07 PM
> To: [email protected] <x-msg://20/[email protected]>
> Subject: Re: [PSES] Digital logic question 
>  
> This message originated outside of DISH and was sent by: 
> [email protected] 
> <x-msg://20/[email protected]> 
> I’m guessing that, as well.  But the entire battery is maybe a foot square 
> and a half-inch thick, and the board is way smaller than that, which makes me 
> think super fast risetimes (relative to clock speed), else traces wouldn’t be 
> long enough to support constructive/destructive interference.
> 
> Ken Javor
> Phone: (256) 650-5261
> 
> 
> From: "Grasso, Charles" <[email protected] 
> <x-msg://20/[email protected]>>
> Reply-To: "Grasso, Charles" <[email protected] 
> <x-msg://20/[email protected]>>
> Date: Mon, 25 Jan 2021 19:02:33 +0000
> To: <[email protected] <x-msg://20/[email protected]>>
> Subject: Re: [PSES] Digital logic question
> 
> Thanks Ken.
> 
> 
> 
> Assuming that this is a faithful representation of the signal is ON the 
> circuit board then there really is a problem 
> with the clock generation and distribution on the board. My guess is that the 
> xmission lines are really long and/or
> improperly terminated. 
> 
> 
> 
> To answer your question regarding the "squaring up" of nasty signals. If the 
> nasty signal is
> valid within the operating input switching characteristics of the logic 
> gates, then the output 
> will be a cleaned up version of the input (esp at 4MHz). 
> 
> 
> 
> Chas
> 
> 
> From: Ken Javor <[email protected] 
> <x-msg://20/[email protected]>>
> Sent: Monday, January 25, 2021 11:30 AM
> To: [email protected] <x-msg://20/[email protected]>
> Subject: Re: [PSES] Digital logic question 
>  
> This message originated outside of DISH and was sent by: 
> [email protected] 
> <x-msg://20/[email protected]> 
> This was measured not on the board, but by draping a very short wire over the 
> equipment plastic case and running that into an o’scope as a troubleshoot. So 
> this is capacitively coupled to the outside.
> 
> <image.png>
> 
> Ken Javor
> Phone: (256) 650-5261
> 
> 
> 
> From: "Grasso, Charles" <[email protected] 
> <x-msg://20/[email protected]>>
> Date: Mon, 25 Jan 2021 18:21:24 +0000
> To: "[email protected] <x-msg://20/[email protected]>" 
> <[email protected] <x-msg://20/[email protected]>>, Ken 
> Javor <[email protected] <x-msg://20/[email protected]>>
> Subject: Re: Digital logic question
> 
> ​When you say damped sine - does the amplitude decrease with time? (I presume 
> that the measurement is at the destination).  Typically there is too much 
> series impedance (filtering?) on the signal.​ 
> From: Ken Javor <[email protected] 
> <x-msg://20/[email protected]>>
> Sent: Monday, January 25, 2021 9:28 AM
> To: [email protected] <x-msg://20/[email protected]>
> Subject: [PSES] Digital logic question 
>  
> This message originated outside of DISH and was sent by: 
> [email protected] 
> <x-msg://20/[email protected]> 
> Have a customer who I suspect has way too fast a risetime for his 
> application.  Clock runs at 4 MHz. I’m seeing an ugly damped sine occurring 
> at 2 MHz rate, leading to broadband outages around 200 MHz. Suspect that a 
> risetime somewhere is being corrupted.
> 
> Is it enough to slow down the clock’s rise and fall times, or do the logic 
> chips fed by the clock act as Schmitt triggers and square things up again if 
> they operate off a fast logic family?
> 
> Thank you,
> 
> Ken Javor
> Phone: (256) 650-5261
> -
> ----------------------------------------------------------------
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