Good points, all – thanks. Ken Javor Phone: (256) 650-5261
From: Joe Randolph <[email protected]> Reply-To: Joe Randolph <[email protected]> Date: Fri, 29 Jan 2021 13:58:32 -0500 To: <[email protected]> Subject: Re: [PSES] Digital logic question I am not an expert in EMC, but I have a pretty good understanding of the basics. I’ve been watching this thread and I want to add a few comments: 1) Radiated emissions from a comparatively slow 4 MHz clock source are a function of two basic parameters: a. The first parameter is “loop area” which is the area of a current loop in which the clock signal travels from the clock’s source to its destination, plus the ground return current that travels from the destination back to that source. Without careful attention to the board layout, these unintentional loops can get very large. The goal should be to minimize the loop area. The situation can get particularly bad on a 2-layer board that has no internal ground plane, but even with a ground plane I have seen some simple mistakes where the ground plane was carved up into various islands without giving thought to the resulting loop area for high speed signals. b. The second parameter is simply the current in the loop. If the clock is a simple clock that has a low impedance source driving a set of high impedance CMOS inputs, there will be some unintentional current pulses created by the interaction of the clock rise/fall times and the parasitic capacitance in the board. For this type of simple clock circuit, it can be very helpful to place a series resistor in the clock output signal line. 2) I think that the use of a series resistor, by itself, should be sufficient to limit the current pulses associated with the rise/fall times of the clock. I would be inclined to avoid adding a shunt capacitor to make an R-C filter, because that creates more opportunities for unintended side effects related to rise/fall times and the ground return path from the capacitor. 3) Regarding rise/fall times, 4 MHz is comparatively slow these days, so any logic family (even 4000 series CMOS) should be sufficient. Some of the faster logic families can actually increase emissions due to a phenomenon called “ground bounce.” So, you have a bad layout, and need a quick fix, using a slower logic family can help. 4) Note that clock noise does not have to come from just the clock signal itself. If there are circuits on the board that are being switched by the clock, the noise could be coming from those circuits rather than the clock itself. Since your clock is 4 MHz and the emissions seem to be harmonics of 2 MHz, look closely at any circuits that are operating at 2 MHz. Based on the description of the problem so far, I suspect that such circuits are the actual cause of the reported problem. 5) Lastly, if you decide to put an R-C filter on the clock (which I don’t recommend, as noted above), it is possible to create problems by making the rise/fall times too slow. If you combine slow rise/fall times with very fast logic, a phenomenon called “meta-stability” can cause the logic to actually oscillate briefly as the slow input signal passes through the transition region on the input. Logic gates that are intentionally designed to operate correctly with slow rise/fall times will be described as having a “Schmitt trigger” input stage. Joe Randolph Telecom Design Consultant Randolph Telecom, Inc. 781-721-2848 (USA) [email protected] <mailto:[email protected]> http://www.randolph-telecom.com <http://www.randolph-telecom.com/> From: Grasso, Charles [Outlook] [mailto:[email protected]] Sent: Tuesday, January 26, 2021 4:20 PM To: [email protected] Subject: Re: [PSES] Digital logic question Agree with Ken (both of them!) Chas From: Ken Javor <[email protected]> Sent: Tuesday, January 26, 2021 2:16 PM To: [email protected] Subject: Re: [PSES] Digital logic question This message originated outside of DISH and was sent by: [email protected] Makes sense. Awaiting test results... Ken Javor Phone: (256) 650-5261 From: Ken Wyatt <[email protected]> Reply-To: Ken Wyatt <[email protected]> Date: Tue, 26 Jan 2021 11:56:58 -0700 To: <[email protected]> Subject: Re: [PSES] Digital logic question I agree. In the early days at HP, we would commonly place a simple low-pass R-C filter after the clock IC (typically, 27 Ohms and 25 pF, or so - calculated at 3dB point of 3 to 5X the clock freq). In fact, with the usual parasitic capacitance, we often could get away with a simple series resistor of low value. After taking some training on automotive EMC from Todd Hubing, he often suggests adding series 1k resistors in ALL the data and address bus lines to slow down edges. Of course, this would apply mainly for slow data rate CAN buses and associated digital logic. Cheers, Ken _______________________ I'm here to help you succeed! Feel free to call or email with any questions related to EMC or EMI troubleshooting - at no obligation. I'm always happy to help! Kenneth Wyatt Wyatt Technical Services LLC 56 Aspen Dr. Woodland Park, CO 80863 Phone: (719) 310-5418 Web Site <http://www.emc-seminars.com> | Blog <https://design-4-emc.com> The EMC Blog (EDN) <https://www.edn.com/electronics-blogs/4376432/The-EMC-Blog> Subscribe to Newsletter <http://www.emc-seminars.com/Newsletter/Newsletter.html> Connect with me on LinkedIn <https://www.linkedin.com/in/kennethwyatt/> > On Jan 26, 2021, at 11:51 AM, Ken Javor <[email protected]> wrote: > > Re: [PSES] Digital logic question > Thanks. Well, the first part will be to check for the corrupted rise/fall > time. With such a slow clock – 4.19 MHz – it seems to me the simple solution > is if the risetime is sub-ten nanoseconds, to simply slow it down with an RC > filter, as opposed to redesigning the board stack-up to provide glitch-free > operation. > > Agree/disagree? > > Ken Javor > Phone: (256) 650-5261 > > > From: Ken Wyatt <[email protected] <x-msg://22/[email protected]> > > Reply-To: Ken Wyatt <[email protected] <x-msg://22/[email protected]> > > > Date: Tue, 26 Jan 2021 11:34:04 -0700 > To: <[email protected] <x-msg://22/[email protected]> > > Subject: Re: [PSES] Digital logic question > > Hi Ken, > > The biggest problem I see when faced with RE issues is that clocks, > data/address buses and other fast-edged signals do not have an adjacent solid > return plane. This is especially important for wireless devices. Have your > client check their stack-up, because invariably, you’ll find, if four layers > (top to bottom), s-g-p-s, with the power and ground return way too far > separated (30 to 40 mils (poor HF decoupling) and with the bottom signal layer > referenced to power, instead of the return plane. > > I discuss this in my four-part article on low EMI design for PC boards: > https://www.edn.com/design-pcbs-for-emi-part-1-how-signals-move/ > > Cheers, Ken > > _______________________ > > I'm here to help you succeed! Feel free to call or email with any questions > related to EMC or EMI troubleshooting - at no obligation. I'm always happy to > help! > > Kenneth Wyatt > Wyatt Technical Services LLC > 56 Aspen Dr. > Woodland Park, CO 80863 > > Phone: (719) 310-5418 > > Web Site <http://www.emc-seminars.com <http://www.emc-seminars.com/> > | Blog > <https://design-4-emc.com <https://design-4-emc.com/> > > The EMC Blog (EDN) > <https://www.edn.com/electronics-blogs/4376432/The-EMC-Blog> > Subscribe to Newsletter > <http://www.emc-seminars.com/Newsletter/Newsletter.html> > Connect with me on LinkedIn <https://www.linkedin.com/in/kennethwyatt/> >> On Jan 26, 2021, at 10:10 AM, Ken Javor <[email protected] >> <x-msg://22/[email protected]> > wrote: >> >> At my request based on this EMC forum back and forth and the specs on the >> processor which is very slow, customer is going to measure clock waveform. >> >> Ken Javor >> Phone: (256) 650-5261 >> >> >> From: "Grasso, Charles" <[email protected] >> <x-msg://22/[email protected]> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > > >> Date: Tue, 26 Jan 2021 16:19:30 +0000 >> To: "[email protected] <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > " <[email protected] >> <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > >, Ken Javor >> <[email protected] <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > > >> Subject: Re: [PSES] Digital logic question >> >> Agreed. Perhaps your customer could take a measurement on the pwa? >> >> >> From: Ken Javor <[email protected] >> <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > > >> Sent: Monday, January 25, 2021 12:07 PM >> To: [email protected] <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > >> Subject: Re: [PSES] Digital logic question >> >> This message originated outside of DISH and was sent by: >> [email protected] >> <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > >> I’m guessing that, as well. But the entire battery is maybe a foot square >> and a half-inch thick, and the board is way smaller than that, which makes me >> think super fast risetimes (relative to clock speed), else traces wouldn’t be >> long enough to support constructive/destructive interference. >> >> Ken Javor >> Phone: (256) 650-5261 >> >> >> From: "Grasso, Charles" <[email protected] >> <x-msg://22/[email protected]> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > > >> Reply-To: "Grasso, Charles" <[email protected] >> <x-msg://22/[email protected]> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > > >> Date: Mon, 25 Jan 2021 19:02:33 +0000 >> To: <[email protected] <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > > >> Subject: Re: [PSES] Digital logic question >> >> Thanks Ken. >> >> >> >> Assuming that this is a faithful representation of the signal is ON the >> circuit board then there really is a problem >> with the clock generation and distribution on the board. My guess is that the >> xmission lines are really long and/or >> improperly terminated. >> >> >> >> To answer your question regarding the "squaring up" of nasty signals. If the >> nasty signal is >> valid within the operating input switching characteristics of the logic >> gates, then the output >> will be a cleaned up version of the input (esp at 4MHz). >> >> >> >> Chas >> >> >> From: Ken Javor <[email protected] >> <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > > >> Sent: Monday, January 25, 2021 11:30 AM >> To: [email protected] <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > >> Subject: Re: [PSES] Digital logic question >> >> This message originated outside of DISH and was sent by: >> [email protected] >> <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > >> This was measured not on the board, but by draping a very short wire over the >> equipment plastic case and running that into an o’scope as a troubleshoot. So >> this is capacitively coupled to the outside. >> >> <image.png> >> >> Ken Javor >> Phone: (256) 650-5261 >> >> >> >> From: "Grasso, Charles" <[email protected] >> <x-msg://22/[email protected]> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > > >> Date: Mon, 25 Jan 2021 18:21:24 +0000 >> To: "[email protected] <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > " <[email protected] >> <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > >, Ken Javor >> <[email protected] <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > > >> Subject: Re: Digital logic question >> >> When you say damped sine - does the amplitude decrease with time? (I presume >> that the measurement is at the destination). Typically there is too much >> series impedance (filtering?) on the signal. >> >> >> From: Ken Javor <[email protected] >> <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > > >> Sent: Monday, January 25, 2021 9:28 AM >> To: [email protected] <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > >> Subject: [PSES] Digital logic question >> >> This message originated outside of DISH and was sent by: >> [email protected] >> <x-msg://22/[email protected]> >> <x-msg://20/[email protected] >> <x-msg://20/[email protected]> > >> Have a customer who I suspect has way too fast a risetime for his >> application. Clock runs at 4 MHz. I’m seeing an ugly damped sine occurring >> at 2 MHz rate, leading to broadband outages around 200 MHz. Suspect that a >> risetime somewhere is being corrupted. >> >> Is it enough to slow down the clock’s rise and fall times, or do the logic >> chips fed by the clock act as Schmitt triggers and square things up again if >> they operate off a fast logic family? >> >> Thank you, >> >> Ken Javor >> Phone: (256) 650-5261 >> - >> ---------------------------------------------------------------- >> >> This message is from the IEEE Product Safety Engineering Society emc-pstc >> discussion list. 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To post a message to the list, send your e-mail to >> <[email protected]> >> >> All emc-pstc postings are archived and searchable on the web at: >> http://www.ieee-pses.org/emc-pstc.html >> >> Attachments are not permitted but the IEEE PSES Online Communities site at >> http://product-compliance.oc.ieee.org/ can be used for graphics (in well-used >> formats), large files, etc. >> >> Website: http://www.ieee-pses.org/ >> Instructions: http://www.ieee-pses.org/list.html (including how to >> unsubscribe) <http://www.ieee-pses.org/list.html> >> List rules: http://www.ieee-pses.org/listrules.html >> >> For help, send mail to the list administrators: >> Scott Douglas <[email protected]> >> Mike Cantwell <[email protected]> >> >> For policy questions, send mail to: >> Jim Bacher <[email protected]> >> David Heald <[email protected]> >> >> - >> ---------------------------------------------------------------- >> This message is from the IEEE Product Safety Engineering Society emc-pstc >> discussion list. To post a message to the list, send your e-mail to >> <[email protected]> >> >> All emc-pstc postings are archived and searchable on the web at: >> http://www.ieee-pses.org/emc-pstc.html >> >> Attachments are not permitted but the IEEE PSES Online Communities site at >> http://product-compliance.oc.ieee.org/ can be used for graphics (in well-used >> formats), large files, etc. >> >> Website: http://www.ieee-pses.org/ >> Instructions: http://www.ieee-pses.org/list.html (including how to >> unsubscribe) <http://www.ieee-pses.org/list.html> >> List rules: http://www.ieee-pses.org/listrules.html >> >> For help, send mail to the list administrators: >> Scott Douglas <[email protected]> >> Mike Cantwell <[email protected]> >> >> For policy questions, send mail to: >> Jim Bacher <[email protected]> >> David Heald <[email protected]> >> - >> ---------------------------------------------------------------- >> >> This message is from the IEEE Product Safety Engineering Society emc-pstc >> discussion list. To post a message to the list, send your e-mail to >> <[email protected]> >> >> All emc-pstc postings are archived and searchable on the web at: >> http://www.ieee-pses.org/emc-pstc.html >> >> Attachments are not permitted but the IEEE PSES Online Communities site at >> http://product-compliance.oc.ieee.org/ can be used for graphics (in well-used >> formats), large files, etc. >> >> Website: http://www.ieee-pses.org/ >> Instructions: http://www.ieee-pses.org/list.html (including how to >> unsubscribe) <http://www.ieee-pses.org/list.html> >> List rules: http://www.ieee-pses.org/listrules.html >> >> For help, send mail to the list administrators: >> Scott Douglas <[email protected]> >> Mike Cantwell <[email protected]> >> >> For policy questions, send mail to: >> Jim Bacher <[email protected]> >> David Heald <[email protected]> >> - ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. To post a message to the list, send your e-mail to <[email protected]> All emc-pstc postings are archived and searchable on the web at: http://www.ieee-pses.org/emc-pstc.html Attachments are not permitted but the IEEE PSES Online Communities site at http://product-compliance.oc.ieee.org/ can be used for graphics (in well-used formats), large files, etc. Website: http://www.ieee-pses.org/ Instructions: http://www.ieee-pses.org/list.html (including how to unsubscribe) List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas <[email protected]> Mike Cantwell <[email protected]> For policy questions, send mail to: Jim Bacher: <[email protected]> David Heald: <[email protected]>
