Clearance concerns dielectric breakdown through air and is strongly influenced 
by peak voltage and transient (impulse) conditions. A 500 V pulse is still a 
500 V peak stress.  IEC 60664 specifically distinguishes working voltage, 
recurring peak voltage, and short-duration transient overvoltage, and 
clearances can be dimensioned against peak or withstand voltage.

 

Creepage means tracking along an insulating surface is affected by the duration 
of voltage stress, contamination, moisture, material CTI and material group.  
IEC 60664 explicitly lists time under voltage stress as one of the factors 
affecting creepage, and its conventional creepage tables are based on long-term 
RMS voltage stress.

 

Between two inaccessible internal conductors, the pin-to-pin insulation may 
instead be functional insulation—provided that failure of that insulation does 
not create another hazard. That's the key issue.

 

I suggest you employ a regulatory consultant or engage services of an NRTL to 
assess.

 

Ralph

 

From: Richard Nute <[email protected]> 
Sent: September 28, 2026 1:19 PM
To: [email protected]
Subject: Re: [PSES] Spacings

 

 

 

Hi Steve:

 

The connector should have electrical ratings, both voltage and current per pin. 
 One question I have is the heating effect of running the same (rated) current 
per pin throughout the connector. – whether this construction is included in 
the ratings. 

 

Since the voltage (and current) are “secondary” circuits, transient voltages 
should be minimum or none.  Therefore, spacings (both C&C) need only be for 
rated voltage, not for transient voltages.  Hi-pot test is rated voltage plus 
some margin.  (Maybe raise the hi-pot test voltage to breakdown to determine 
the margin.)

 

Best regards,

Rich

 

Note:  The IEEE is doing away with my [email protected] <mailto:[email protected]>  
e-mail forwarding address.  My fall-back e-mail address is 
[email protected] <mailto:[email protected]> .

 

 

 

From: Steve Brody <[email protected] 
<mailto:[email protected]> > 
Sent: Sunday, September 27, 2026 7:13 PM
To: [email protected] <mailto:[email protected]> 
Subject: [PSES] Spacings

 

Hi experts, 

  

I have a client who is using a cable with a 50 pin connector carrying 500VDC at 
1 ms bursts to one pin at a time. 25 of the pins are ground, and the other 25 
are used for the DC voltage.  The odd number pins are used for the ground nd 
the even numbered pins are dc. 

  

There is another cable configured in the same manner, but this one has 300VDMS 
and ground.  The AC is also for a short bursts of time but I  

don't know the timing. 

  

Does the fact that the voltages are not continuous reduce the C&C?  Can a hypot 
test be used to confirm that there is not a problem even if the C&C are less 
than Appendix K? 

  

Both the AC and DC are derived from several circuits, but they come from an 
approved AC SMPS that will fold back should there be a short and then recover. 

  

None of the voltages are accessible. 

  

Thanks, 

  

Steve Brody 

[email protected] <mailto:[email protected]>  

C - 603 617 9116 

 

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