Hi Seb

On Wednesday 02 May 2007 11:39, Seb James wrote:
> Mesa 5i20 board which provides 2 axes of servo/encoder control, 31
> channels of logic input and 29 channels of logic output.

Nothing too dificult there - IO is currently defined as 24 bits in at most, 
half a dozen places. Mapping the internal connections to physical pins would 
be the bulk of any work.

> I think this is a case of modifying the hostmot4 configuration, and then
> updating the hal_m5i20.c driver to suit the new fpga configuration.

Applying a couple of new constraints in the driver would expose the extra IO, 
again, nothing too taxing there. The worst part is the notion that firmware 
*has* to be embedded in the module or some untrusted user space utility is 
required to preload the fpga - The kernel already provides a mechanism for 
firmware loading without resorting to NIMBY code.

A few minutes with a text editor would see the changes you need in place. To 
rework the driver so that it does the right thing wrt firmware would take a 
little longer.


Regards, Paul.

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