Eric H. Johnson wrote:
> I am not sure what you mean by the FPGA register. Do you mean the interface
> register between the driver and the m5i20, or the register actually handling
> the PWM within the FPGA? As I said in an earlier email (off list), I concur
> that the value being sent to the FPGA through the interface register is
> correct (providing the bit shift to bits 16-27 is where the value is
> supposed to go), which would confirm that my pwmgen.scale is set to 1.0.
By "FPGA register" i mean the register on the 5i20 board where the
driver on the PC tells the 5i20 what PWM duty cycle it wants. I think
this means both of the things you described.
Ok so we're in agreement that the proper PWM value is being requested of
the 5i20 board, and the question now is whether the FPGA outputs the
proper PWM signal.
> I was able to measure the duty cycle on a pain old multi-meter. At values of
> 0.125 and below, the voltage would start dropping from the almost 100% duty
> cycle voltage of just under 3.3V, and very linearly for the range of 0.125
> down to 0.0. The voltage reading from my meter was in fact very accurate.
It is my understanding that a normal voltage meter is not a reliable
tool for measuring the pulse width of a PWM signal.
I'll see if I can borrow an oscilloscope from work...
--
Sebastian Kuzminsky
Theo: "Julian? I haven't seen you in twenty years. You look good.
The picture the police have of you doesn't do you justice."
Julian: "What do the police know about justice?"
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